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Searched refs:MSR_IA32_TSC (Results 1 – 12 of 12) sorted by relevance

/linux/tools/testing/selftests/kvm/x86/
H A Dtsc_msrs_test.c3 * Tests for MSR_IA32_TSC and MSR_IA32_TSC_ADJUST.
23 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val); in guest_code()
26 /* Guest: writes to MSR_IA32_TSC affect both MSRs. */ in guest_code()
28 wrmsr(MSR_IA32_TSC, val); in guest_code()
29 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val); in guest_code()
36 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), val); in guest_code()
41 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val); in guest_code()
51 GUEST_ASSERT_EQ(rounded_rdmsr(MSR_IA32_TSC), HOST_ADJUST + val); in guest_code()
55 * Guest: writes to MSR_IA32_TSC affect both MSRs, so the host-side in guest_code()
60 wrmsr(MSR_IA32_TSC, va in guest_code()
[all...]
H A Dvmx_tsc_adjust_test.c68 wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE); in l2_guest_code()
83 wrmsr(MSR_IA32_TSC, rdtsc() - TSC_ADJUST_VALUE); in l1_guest_code()
H A Dvmx_nested_tsc_scaling_test.c65 tsc_start = rdmsr(MSR_IA32_TSC); in check_tsc_freq()
67 tsc_end = rdmsr(MSR_IA32_TSC); in check_tsc_freq()
H A Dtsc_scaling_sync.c57 vcpu_set_msr(vcpu, MSR_IA32_TSC, TEST_TSC_OFFSET); in run_vcpu()
/linux/arch/x86/include/asm/
H A Dmsr-index.h884 #define MSR_IA32_TSC 0x00000010 macro
/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h877 #define MSR_IA32_TSC 0x00000010 macro
/linux/arch/x86/coco/sev/
H A Dvc-handle.c372 * accesses of MSR_IA32_TSC and MSR_AMD64_GUEST_TSC_FREQ.
386 * Writes: Writing to MSR_IA32_TSC can cause subsequent reads of the TSC in __vc_handle_secure_tsc_msrs()
389 * Reads: Reads of MSR_IA32_TSC should return the current TSC value, use in __vc_handle_secure_tsc_msrs()
416 case MSR_IA32_TSC: in vc_handle_msr()
/linux/tools/testing/selftests/kvm/include/x86/
H A Dprocessor.h1136 return msr != MSR_IA32_TSC; in is_durable_msr()
/linux/arch/x86/kvm/vmx/
H A Dnested.c1024 if (msr_index == MSR_IA32_TSC) { in nested_vmx_get_vmexit_msr_value()
1026 MSR_IA32_TSC); in nested_vmx_get_vmexit_msr_value()
2633 prepare_vmx_msr_autostore_list(&vmx->vcpu, MSR_IA32_TSC); in prepare_vmcs02_rare()
H A Dvmx.c4076 vmx_disable_intercept_for_msr(vcpu, MSR_IA32_TSC, MSR_TYPE_R); in vmx_recalc_msr_intercepts()
/linux/arch/x86/kvm/
H A Dx86.c327 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
3953 case MSR_IA32_TSC: in kvm_set_msr_common()
4274 case MSR_IA32_TSC: { in kvm_get_msr_common()
4276 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset in kvm_get_msr_common()
H A Demulate.c3221 ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc); in em_rdtsc()