Searched refs:IMX6QDL_CLK_IPU1_DI1_PRE_SEL (Results 1 – 3 of 3) sorted by relevance
45 #define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36 macro
401 <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
664 hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); in imx6q_clocks_init() 933 clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk); in imx6q_clocks_init()