Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 – 7 of 7) sorted by relevance
| /linux-3.3/drivers/net/wireless/ath/ath9k/ |
| D | ar9002_calib.c | 57 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
77 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
90 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
247 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
250 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
259 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
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| D | ar9002_phy.c | 243 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
251 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
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| D | ar9002_phy.h | 185 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) macro
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| D | eeprom_9287.c | 940 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_ar9287_set_board_values()
941 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values()
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| D | eeprom_4k.c | 767 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_4k_set_gain()
768 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ath9k_hw_4k_set_gain()
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| D | eeprom_def.c | 563 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
564 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_def_set_board_values()
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| D | ar5008_phy.c | 308 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
314 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
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