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Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_uvd.h32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro
38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
H A Dvcn_v5_0_1.c379 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_1_mc_resume()
460 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
785 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_1_start_sriov()
H A Duvd_v4_2.c580 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
H A Duvd_v3_1.c246 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
H A Duvd_v5_0.c291 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v5_0_mc_resume()
H A Dvcn_v4_0_3.c486 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_mc_resume()
574 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1063 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c483 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
561 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_start_sriov()
H A Dvcn_v5_0_0.c400 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_0_mc_resume()
479 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v2_5.c646 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()
714 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1484 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
H A Dvcn_v3_0.c552 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()
620 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1462 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
H A Duvd_v7_0.c699 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_mc_resume()
841 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_sriov_start()
H A Dvcn_v4_0_5.c433 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_5_mc_resume()
514 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v1_0.c369 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v1_0_mc_resume_spg_mode()
440 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
H A Dvcn_v2_0.c414 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()
484 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
H A Duvd_v6_0.c615 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v6_0_mc_resume()