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Searched refs:upper_32_bits (Results 1 – 25 of 673) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c71 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8) in pm_map_process_v9()
75 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
79 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v9()
84 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
132 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8); in pm_map_process_aldebaran()
134 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); in pm_map_process_aldebaran()
138 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_aldebaran()
143 upper_32_bits(vm_page_table_base_addr); in pm_map_process_aldebaran()
186 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v9()
213 packet->gws_mask_hi = upper_32_bits(re in pm_set_resources_v9()
[all...]
H A Dkfd_packet_manager_vi.c71 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_vi()
110 packet->bitfields3.ib_base_hi = upper_32_bits(ib); in pm_runlist_vi()
135 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_vi()
138 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
190 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
196 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
264 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_vi()
266 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_vi()
294 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_vi()
H A Dkfd_mqd_manager_v12.c129 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
154 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
195 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
198 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
200 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
222 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
337 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
339 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd_sdma()
/linux/drivers/gpu/drm/radeon/
H A Dsi_dma.c82 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
83 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
121 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
133 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
173 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages()
177 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages()
265 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
266 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
H A Devergreen_dma.c48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
142 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
143 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
H A Dni_dma.c134 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
222 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
330 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
331 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
370 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
382 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages()
422 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages()
426 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
H A Dr600_dma.c143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
295 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
322 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
360 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
415 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
426 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
478 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
479 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
H A Dcik_sdma.c145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
208 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
237 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
400 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
614 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
616 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
670 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
728 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test()
817 ib->ptr[ib->length_dw++] = upper_32_bits(sr in cik_sdma_vm_copy_pages()
[all...]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c91 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
115 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
122 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
123 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence()
170 WREG32(mmDMA_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
231 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
284 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
332 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
333 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
355 ib->ptr[ib->length_dw++] = upper_32_bits(p in si_dma_vm_write_pte()
[all...]
H A Dsdma_v7_0.c151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_init_cond_exec()
216 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", in sdma_v7_0_ring_set_wptr()
219 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
233 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
241 upper_32_bits(ring->wptr << 2)); in sdma_v7_0_ring_set_wptr()
290 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v7_0_ring_emit_ib()
293 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v7_0_ring_emit_ib()
369 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
380 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v7_0_ring_emit_fence()
381 amdgpu_ring_write(ring, upper_32_bits(se in sdma_v7_0_ring_emit_fence()
[all...]
H A Dsdma_v6_0.c151 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_init_cond_exec()
214 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", in sdma_v6_0_ring_set_wptr()
217 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
231 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
237 upper_32_bits(ring->wptr << 2)); in sdma_v6_0_ring_set_wptr()
286 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v6_0_ring_emit_ib()
289 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v6_0_ring_emit_ib()
365 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
376 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v6_0_ring_emit_fence()
377 amdgpu_ring_write(ring, upper_32_bits(se in sdma_v6_0_ring_emit_fence()
[all...]
H A Dsdma_v5_2.c150 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_init_cond_exec()
220 "upper_32_bits(ring->wptr << 2) == 0x%08x\n", in sdma_v5_2_ring_set_wptr()
223 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
238 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
247 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
251 upper_32_bits(ring->wptr << 2)); in sdma_v5_2_ring_set_wptr()
300 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_2_ring_emit_ib()
303 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_2_ring_emit_ib()
383 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_2_ring_emit_fence()
394 amdgpu_ring_write(ring, upper_32_bits(add in sdma_v5_2_ring_emit_fence()
[all...]
H A Dsdma_v2_4.c261 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
314 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
322 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
323 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
445 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); in sdma_v2_4_gfx_resume()
555 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
610 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
664 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v2_4_vm_copy_pte()
666 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_copy_pte()
689 ib->ptr[ib->length_dw++] = upper_32_bits(p in sdma_v2_4_vm_write_pte()
[all...]
H A Damdgpu_cper.c298 reg_data.status_hi = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ue_record()
300 reg_data.addr_hi = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ue_record()
302 reg_data.ipid_hi = upper_32_bits(bank->regs[ACA_REG_IDX_IPID]); in amdgpu_cper_generate_ue_record()
304 reg_data.synd_hi = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]); in amdgpu_cper_generate_ue_record()
392 reg_data[CPER_ACA_REG_CTL_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CTL]); in amdgpu_cper_generate_ce_records()
394 reg_data[CPER_ACA_REG_STATUS_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_STATUS]); in amdgpu_cper_generate_ce_records()
396 reg_data[CPER_ACA_REG_ADDR_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_ADDR]); in amdgpu_cper_generate_ce_records()
398 reg_data[CPER_ACA_REG_MISC0_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_MISC0]); in amdgpu_cper_generate_ce_records()
400 reg_data[CPER_ACA_REG_CONFIG_HI] = upper_32_bits(bank->regs[ACA_REG_IDX_CONFIG]); in amdgpu_cper_generate_ce_records()
402 reg_data[CPER_ACA_REG_IPID_HI] = upper_32_bits(ban in amdgpu_cper_generate_ce_records()
[all...]
H A Dsdma_v5_0.c310 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_init_cond_exec()
380 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", in sdma_v5_0_ring_set_wptr()
383 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
397 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
403 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
452 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
455 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
533 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
544 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
545 amdgpu_ring_write(ring, upper_32_bits(se in sdma_v5_0_ring_emit_fence()
[all...]
/linux/drivers/pci/controller/mobiveil/
H A Dpcie-mobiveil.c154 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ib_windows()
159 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ib_windows()
164 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ib_windows()
195 mobiveil_csr_writel(pcie, upper_32_bits(size64), in program_ob_windows()
205 mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr), in program_ob_windows()
210 mobiveil_csr_writel(pcie, upper_32_bits(pci_addr), in program_ob_windows()
/linux/drivers/iio/test/
H A Diio-test-format.c212 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
218 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
224 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
230 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
236 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
242 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
248 values[1] = upper_32_bits(value); in iio_test_iio_format_value_integer_64()
/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dring.c28 dma_h = upper_32_bits(next_dma); in xge_setup_desc()
40 xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr)); in xge_update_tx_desc_addr()
52 xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr)); in xge_update_rx_desc_addr()
/linux/drivers/pci/controller/
H A Dpci-xgene.c296 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16); in xgene_pcie_set_ib_mask()
300 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16); in xgene_pcie_set_ib_mask()
386 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr)); in xgene_pcie_setup_ob_reg()
388 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask)); in xgene_pcie_setup_ob_reg()
390 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr)); in xgene_pcie_setup_ob_reg()
398 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr)); in xgene_pcie_setup_cfg_reg()
448 upper_32_bits(pim) | EN_COHERENCY); in xgene_pcie_setup_pims()
450 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size)); in xgene_pcie_setup_pims()
507 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); in xgene_pcie_setup_ib_reg()
517 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_add in xgene_pcie_setup_ib_reg()
[all...]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgm20b.c74 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
77 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
80 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
104 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
105 .data_dma_base1 = upper_32_bits(data), in gm20b_pmu_acr_bld_write()
106 .overlay_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgv100.c48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd)); in gv100_chan_ramfc_write()
52 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); in gv100_chan_ramfc_write()
102 nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr)); in gv100_ectx_bind()
122 nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2)); in gv100_ectx_ce_bind()
188 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); in gv100_runl_insert_chan()
190 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); in gv100_runl_insert_chan()
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgm20b.c42 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
45 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
66 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
67 .data_dma_base1 = upper_32_bits(data), in gm20b_gr_acr_bld_write()
/linux/drivers/media/pci/pt3/
H A Dpt3_dma.c54 iowrite32(upper_32_bits(adap->desc_buf[0].b_addr), in pt3_start_dma()
185 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
191 d->addr_h = upper_32_bits(data_addr); in pt3_alloc_dmabuf()
196 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
205 d->next_h = upper_32_bits(desc_addr); in pt3_alloc_dmabuf()
/linux/include/linux/
H A Dgoldfish.h25 gf_iowrite32(upper_32_bits(addr), porth); in gf_write_ptr()
35 gf_iowrite32(upper_32_bits(addr), porth); in gf_write_dma_addr()
/linux/arch/x86/include/asm/
H A Dmshyperv.h95 u32 input_address_hi = upper_32_bits(input_address); in hv_do_hypercall()
97 u32 output_address_hi = upper_32_bits(output_address); in hv_do_hypercall()
139 u32 input1_hi = upper_32_bits(input1); in _hv_do_fast_hypercall8()
189 u32 input1_hi = upper_32_bits(input1); in _hv_do_fast_hypercall16()
191 u32 input2_hi = upper_32_bits(input2); in _hv_do_fast_hypercall16()

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