| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.c | 74 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
90 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
97 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
113 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
115 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
119 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream()
127 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
128 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
134 pipe_ctx->stream_res in update_dsc_on_stream()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_dio.c | 42 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
52 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
62 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
74 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle); in setup_dio_stream_encoder()
82 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in reset_dio_stream_encoder()
103 pipe_ctx->stream_res.stream_enc->id, in reset_dio_stream_encoder()
114 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_attribute()
121 pipe_ctx->stream_res.tg->inst, in setup_dio_stream_attribute()
136 pipe_ctx->stream_res.audio != NULL); in setup_dio_stream_attribute()
254 pipe_ctx->stream_res in setup_dio_audio_output()
[all...] |
| H A D | link_hwss_hpo_dp.c | 37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder()
92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_attribute()
181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output()
182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output()
189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet()
190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet()
195 if (pipe_ctx->stream_res in disable_hpo_dp_audio_packet()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 96 pipes[i]->stream_res.tg->funcs->disable_crtc(pipes[i]->stream_res.tg); in dp_retrain_link_dp_test()
106 &pipes[i]->stream_res.pix_clk_params, in dp_retrain_link_dp_test()
110 if (pipes[i]->stream_res.audio != NULL) { in dp_retrain_link_dp_test()
115 pipes[i]->stream_res.audio->inst); in dp_retrain_link_dp_test()
117 pipes[i]->stream_res.audio->funcs->az_configure( in dp_retrain_link_dp_test()
118 pipes[i]->stream_res.audio, in dp_retrain_link_dp_test()
125 pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio && in dp_retrain_link_dp_test()
127 pipes[i]->stream_res.audio->funcs->az_disable_hbr_audio(pipes[i]->stream_res in dp_retrain_link_dp_test()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| H A D | dce110_hwseq.c | 637 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
647 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
649 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
651 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame()
652 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
654 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
656 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
657 pipe_ctx->stream_res in dce110_update_info_frame()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ |
| H A D | dcn31_hwseq.c | 385 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
395 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
396 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
397 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
399 if (pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame()
400 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dcn31_update_info_frame()
401 pipe_ctx->stream_res.hpo_dp_stream_enc, in dcn31_update_info_frame()
402 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
404 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame()
405 pipe_ctx->stream_res in dcn31_update_info_frame()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 88 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
607 struct dc *dc = pipe_ctx->stream_res.opp->ctx->dc; in dcn401_set_mcm_luts()
658 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_set_output_transfer_func()
726 opp_inst[i] = opp_heads[i]->stream_res.opp->inst; in enable_stream_timing_calc()
774 dc->res_pool->dccg, pipe_ctx->stream_res.tg->inst, in dcn401_enable_stream_timing()
783 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn401_enable_stream_timing()
784 pipe_ctx->stream_res.tg, in dcn401_enable_stream_timing()
792 dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst); in dcn401_enable_stream_timing()
799 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res in dcn401_enable_stream_timing()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| H A D | dcn10_hwseq.c | 111 !pipe_ctx->stream_res.tg || in dcn10_wait_for_pipe_update_if_needed()
112 !pipe_ctx->stream_res.stream_enc) in dcn10_wait_for_pipe_update_if_needed()
122 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_wait_for_pipe_update_if_needed()
184 !pipe_ctx->stream_res.tg || in dcn10_set_wait_for_update_needed_for_pipe()
185 !pipe_ctx->stream_res.stream_enc) in dcn10_set_wait_for_update_needed_for_pipe()
194 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_set_wait_for_update_needed_for_pipe()
231 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
781 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
1164 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res in dcn10_enable_stream_timing()
3111 struct stream_resource *stream_res = &pipe_ctx->stream_res; dcn10_blank_pixel_data() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 409 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
445 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
481 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
552 if (pipe_ctx->stream_res.opp && in dcn32_set_input_transfer_func()
553 pipe_ctx->stream_res.opp->ctx && in dcn32_set_input_transfer_func()
565 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
1013 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream()
1042 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
1049 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res in dcn32_update_dsc_on_stream()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
| H A D | dce_hwseq.c | 56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 679 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
682 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; in update_psp_stream_config()
685 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; in update_psp_stream_config()
688 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; in update_psp_stream_config()
807 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream()
848 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
850 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
855 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in link_set_dsc_on_stream()
864 DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_enc->id); in link_set_dsc_on_stream()
866 if (pipe_ctx->stream_res in link_set_dsc_on_stream()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ |
| H A D | dcn201_hwseq.c | 310 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
319 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
324 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
345 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
385 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
431 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc()
521 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
542 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
544 pipe->stream_res in dcn201_pipe_control_lock()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1428 params = &opp_heads[i]->stream_res.test_pattern_params; in resource_build_test_pattern_params()
2149 if (otg_master->stream_res.tg) in resource_get_odm_slice_dst_width()
2151 otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) || in resource_get_odm_slice_dst_width()
2191 struct output_pixel_processor *opp = opp_head->stream_res.opp; in resource_get_odm_slice_src_rect()
2268 if (opp_head_a->stream_res.opp != opp_head_b->stream_res.opp) in resource_is_odm_topology_changed()
2311 pipe->stream_res.opp->inst, in resource_log_pipe()
2312 pipe->stream_res.tg->inst); in resource_log_pipe()
2318 pipe->stream_res.opp->inst, in resource_log_pipe()
2319 pipe->stream_res in resource_log_pipe()
[all...] |
| H A D | dc.c | 413 if (pipe->stream == stream && pipe->stream_res.tg) { in set_long_vtotal()
475 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
512 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_get_last_used_drr_vtotal()
516 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { in dc_stream_get_last_used_drr_vtotal()
517 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); in dc_stream_get_last_used_drr_vtotal()
586 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_crc_window()
652 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_multiple_crc_window()
731 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
773 tg = pipe->stream_res in dc_stream_get_crc()
[all...] |
| H A D | dc_hw_sequencer.c | 694 if (pipe_ctx && pipe_ctx->stream_res.tg && in set_drr_and_clear_adjust_pending()
695 pipe_ctx->stream_res.tg->funcs->set_drr) in set_drr_and_clear_adjust_pending()
696 pipe_ctx->stream_res.tg->funcs->set_drr( in set_drr_and_clear_adjust_pending()
697 pipe_ctx->stream_res.tg, params); in set_drr_and_clear_adjust_pending()
863 block_sequence[*num_steps].params.set_output_csc_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
870 block_sequence[*num_steps].params.set_ocsc_default_params.opp_id = current_mpc_pipe->stream_res.opp->inst; in hwss_build_fast_sequence()
1027 if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) in hwss_program_manual_trigger()
1028 pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); in hwss_program_manual_trigger()
1162 hws->funcs.wait_for_blank_complete(opp_head->stream_res in hwss_wait_for_all_blank_complete()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ |
| H A D | dcn21_hwseq.c | 181 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
214 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
215 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe()
248 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
249 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce60/ |
| H A D | dce60_hwseq.c | 128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc()
192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility()
200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color()
251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler()
260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler()
261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1238 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1254 else if (pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing) || opp_cnt == 2) in get_pixel_clock_parameters()
1264 if ((pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container && in get_pixel_clock_parameters()
1265 pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&pipe_ctx->stream->timing)) || in get_pixel_clock_parameters()
1284 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dcn20_build_pipe_pix_clk_params()
1287 &pipe_ctx->stream_res.pix_clk_params, in dcn20_build_pipe_pix_clk_params()
1332 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1393 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1396 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
1399 if (!pipe_ctx->stream_res in dcn20_add_dsc_to_stream_resource()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 223 old_pipe->stream_res.tg == new_pipe->stream_res.tg && in dcn35_disable_otg_wa()
228 new_pipe->stream_res.stream_enc && in dcn35_disable_otg_wa()
229 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && in dcn35_disable_otg_wa()
230 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); in dcn35_disable_otg_wa()
243 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn35_disable_otg_wa()
244 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res in dcn35_disable_otg_wa()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.c | 180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 895 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
919 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
922 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1137 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1141 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1152 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1160 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1170 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1171 pipe_ctx->stream_res in dce110_acquire_underlay()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 82 cmd.replay_enable.data.hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; in dmub_replay_enable()
178 if (pipe_ctx->stream_res.hpo_dp_stream_enc) in dmub_replay_copy_settings()
179 copy_settings_data->hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; in dmub_replay_copy_settings()
192 if (pipe_ctx->stream_res.tg) in dmub_replay_copy_settings()
193 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_replay_copy_settings()
|
| H A D | dmub_psr.c | 347 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings()
348 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
351 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings()
352 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 118 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn316_disable_otg_wa()
119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 131 if (pipe->stream_res.dsc) in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
134 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
148 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
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