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Searched refs:rcc (Results 1 – 25 of 49) sorted by relevance

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/linux/arch/arm/boot/dts/st/
H A Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_C
543 rcc: reset-clock-controller@58024400 { global() label
[all...]
H A Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
106 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
128 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
150 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
188 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
224 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
238 clocks = <&rcc
657 rcc: rcc@40023800 { global() label
[all...]
H A Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc
688 rcc: rcc@40023800 { global() label
[all...]
H A Dstm32mp131.dtsi142 clocks = <&rcc TIM2_K>;
177 clocks = <&rcc TIM3_K>;
213 clocks = <&rcc TIM4_K>;
247 clocks = <&rcc TIM5_K>;
283 clocks = <&rcc TIM6_K>;
308 clocks = <&rcc TIM7_K>;
332 clocks = <&rcc LPTIM1_K>;
375 clocks = <&rcc SPI2_K>;
376 resets = <&rcc SPI2_R>;
400 clocks = <&rcc SPI3_
783 rcc: rcc@50000000 { global() label
[all...]
H A Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
H A Dstm32f769.dtsi15 resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
16 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
24 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
30 clocks = <&rcc 1 CLK_F769_DSI>, <&clk_hse>;
32 resets = <&rcc STM32F7_APB2_RESET(DSI)>;
H A Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp153.dtsi41 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
55 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
H A Dstm32mp135.dtsi15 resets = <&rcc DCMIPP_R>;
16 clocks = <&rcc DCMIPP_K>;
28 clocks = <&rcc LTDC_PX>;
H A Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc
[all...]
H A Dstm32mp157f-dk2-scmi.dtsi52 clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
72 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
98 &rcc {
99 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32mp151c-mecio1r0.dts44 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL3_Q>;
45 assigned-clock-parents = <&rcc PLL3_Q>;
H A Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
141 clocks = <&rcc
[all...]
H A Dstm32mp151c-plyaqm.dts235 clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
250 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
265 &rcc {
266 compatible = "st,stm32mp1-rcc-secure", "syscon";
H A Dstm32f469.dtsi11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
H A Dstm32mp13xc.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
H A Dstm32mp15xc.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
H A Dstm32mp13xf.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
H A Dstm32mp15xf.dtsi12 clocks = <&rcc CRYP1>;
13 resets = <&rcc CRYP1_R>;
H A Dstm32mp157c-odyssey.dts39 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
40 assigned-clock-parents = <&rcc PLL4_P>;
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp231.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
9 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
232 clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>;
234 resets = <&rcc SPI2_R>;
248 clocks = <&rcc CK_KER_SPI2>;
249 resets = <&rcc SPI2_R>;
262 clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>;
264 resets = <&rcc SPI3_
774 rcc: clock-controller@44200000 { global() label
[all...]
H A Dstm32mp251.dtsi6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
238 clocks = <&rcc CK_BUS_OSPIIOM>,
242 resets = <&rcc OSPIIOM_R>,
299 clocks = <&rcc CK_KER_TIM2>;
330 clocks = <&rcc CK_KER_TIM3>;
361 clocks = <&rcc CK_KER_TIM4>;
392 clocks = <&rcc CK_KER_TIM5>;
423 clocks = <&rcc CK_KER_TIM6>;
448 clocks = <&rcc CK_KER_TIM
1675 rcc: clock-controller@44200000 { global() label
[all...]
H A Dstm32mp233.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;
H A Dstm32mp253.dtsi58 clocks = <&rcc CK_ETH2_MAC>,
59 <&rcc CK_ETH2_TX>,
60 <&rcc CK_ETH2_RX>,
61 <&rcc CK_KER_ETH2PTP>,
62 <&rcc CK_ETH2_STP>,
63 <&rcc CK_KER_ETH2>;

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