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Searched refs:port_clock (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
H A Dintel_ddi_buf_trans.c1306 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1335 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1360 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1385 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1412 if (crtc_state->port_clock > 270000) { in tgl_get_combo_buf_trans_dp()
1431 if (crtc_state->port_clock > 540000) { in tgl_get_combo_buf_trans_edp()
1463 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1476 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1507 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1518 if (crtc_state->port_clock > 54000 in rkl_get_combo_buf_trans_edp()
[all...]
H A Dintel_cx0_phy.c430 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
431 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
444 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
445 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
2061 bool is_dp, int port_clock, in intel_c10pll_calc_state_from_table() argument
2067 if (port_clock == tables[i]->clock) { in intel_c10pll_calc_state_from_table()
2092 crtc_state->port_clock, in intel_c10pll_calc_state()
2100 crtc_state->port_clock); in intel_c10pll_calc_state()
2253 if (crtc_state->port_clock < 25175 || crtc_state->port_clock > 60000 in intel_c20_compute_hdmi_tmds_pll()
2626 intel_c20_pll_program(struct intel_display * display,struct intel_encoder * encoder,const struct intel_c20pll_state * pll_state,bool is_dp,int port_clock) intel_c20_pll_program() argument
2756 intel_program_port_clock_ctl(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state,bool is_dp,int port_clock,bool lane_reversal) intel_program_port_clock_ctl() argument
3013 __intel_cx0pll_enable(struct intel_encoder * encoder,const struct intel_cx0pll_state * pll_state,bool is_dp,int port_clock,int lane_count) __intel_cx0pll_enable() argument
3632 int port_clock = 162000; intel_cx0_pll_power_save_wa() local
[all...]
H A Dintel_dpll.c431 int port_clock; in i9xx_crtc_clock_get() local
473 port_clock = pnv_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
475 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
504 port_clock = i9xx_calc_dpll_params(refclk, &clock); in i9xx_crtc_clock_get()
509 * port_clock to compute adjusted_mode.crtc_clock in the in i9xx_crtc_clock_get()
512 crtc_state->port_clock = port_clock; in i9xx_crtc_clock_get()
540 crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); in vlv_crtc_clock_get()
574 crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); in chv_crtc_clock_get()
983 crtc_state->port_clock, refcl in bxt_find_best_dpll()
[all...]
H A Dintel_pmdemand.c172 enum pipe pipe, int port_clock) in intel_pmdemand_update_port_clock() argument
177 pmdemand_state->ddi_clocks[pipe] = port_clock; in intel_pmdemand_update_port_clock()
193 new_crtc_state->port_clock); in intel_pmdemand_update_max_ddiclk()
312 if (new_crtc_state->port_clock != old_crtc_state->port_clock) in intel_pmdemand_needs_update()
H A Dintel_alpm.c134 static int _lnl_compute_aux_less_wake_time(int port_clock) in _lnl_compute_aux_less_wake_time() argument
141 /* port_clock is link rate in 10kbit/s units */ in _lnl_compute_aux_less_wake_time()
142 int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; in _lnl_compute_aux_less_wake_time()
160 _lnl_compute_aux_less_wake_time(crtc_state->port_clock); in _lnl_compute_aux_less_alpm_params()
164 if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, in _lnl_compute_aux_less_alpm_params()
H A Dintel_pmdemand.h28 enum pipe pipe, int port_clock);
H A Dintel_ddi.c267 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
302 static u32 ddi_buf_phy_link_rate(int port_clock) in ddi_buf_phy_link_rate() argument
304 switch (port_clock) { in ddi_buf_phy_link_rate()
322 MISSING_CASE(port_clock); in ddi_buf_phy_link_rate()
327 static int dp_phy_lane_stagger_delay(int port_clock) in dp_phy_lane_stagger_delay() argument
333 * the provided port_clock (aka link clock) corresponding to this delay in dp_phy_lane_stagger_delay()
342 * port_clock (10 kHz) -> bits / 100 us in dp_phy_lane_stagger_delay()
346 return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000); in dp_phy_lane_stagger_delay()
373 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
[all...]
H A Dg4x_dp.c84 if (pipe_config->port_clock == divisor[i].dot) { in g4x_dp_set_clock()
103 pipe_config->port_clock, in intel_dp_prepare()
206 pipe_config->port_clock); in ilk_edp_pll_on()
210 if (pipe_config->port_clock == 162000) in ilk_edp_pll_on()
396 pipe_config->port_clock = 162000; in intel_dp_get_config()
398 pipe_config->port_clock = 270000; in intel_dp_get_config()
402 intel_dotclock_calculate(pipe_config->port_clock, in intel_dp_get_config()
H A Dintel_audio.c248 crtc_state->port_clock == hdmi_ncts_table[i].clock) { in audio_config_hdmi_get_n()
469 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
507 link_clk = crtc_state->port_clock; in calc_samples_room()
784 crtc_state->port_clock, in intel_audio_codec_enable()
1010 crtc_state->port_clock >= 540000 && in intel_audio_min_cdclk()
1037 min_cdclk = max(min_cdclk, crtc_state->port_clock); in intel_audio_min_cdclk()
H A Dintel_dpll_mgr.c1049 hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p); in hsw_ddi_wrpll_compute_dpll()
1056 crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL, in hsw_ddi_wrpll_compute_dpll()
1079 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_compute_dpll()
1099 int clock = crtc_state->port_clock; in hsw_ddi_lcpll_get_dpll()
1156 if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000)) in hsw_ddi_spll_compute_dpll()
1817 ret = skl_ddi_calculate_wrpll(crtc_state->port_clock, in skl_ddi_hdmi_pll_dividers()
1842 crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL, in skl_ddi_hdmi_pll_dividers()
1859 switch (crtc_state->port_clock / 2) { in skl_ddi_dp_set_dpll_hw_state()
2282 if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) { in bxt_ddi_dp_pll_dividers()
2291 clk_div->dot != crtc_state->port_clock); in bxt_ddi_dp_pll_dividers()
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H A Dintel_dp_mst.c172 return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72, in intel_dp_mst_max_dpt_bpp()
216 crtc_state->port_clock, in intel_dp_mst_compute_m_n()
290 mst_state->pbn_div = drm_dp_get_vc_payload_bw(crtc_state->port_clock, in intel_dp_mtp_tu_compute_config()
447 crtc_state->port_clock = limits->max_rate; in mst_stream_compute_link_config()
511 crtc_state->port_clock = limits->max_rate; in mst_stream_dsc_compute_link_config()
1178 crtc_state->port_clock, crtc_state->lane_count)) in intel_mst_reprobe_topology()
1184 crtc_state->port_clock, crtc_state->lane_count); in intel_mst_reprobe_topology()
H A Dintel_dpio_phy.c983 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
985 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
987 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
989 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
H A Dvlv_dsi_pll.c205 config->port_clock = pclk; in vlv_dsi_pll_compute()
526 config->port_clock = pclk; in bxt_dsi_pll_compute()
H A Dintel_dp.c147 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
1606 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, in intel_dp_compute_rate() argument
1612 if (display->platform.g4x && port_clock == 268800) in intel_dp_compute_rate()
1613 port_clock = 270000; in intel_dp_compute_rate()
1619 intel_dp_rate_select(intel_dp, port_clock); in intel_dp_compute_rate()
1621 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); in intel_dp_compute_rate()
1802 pipe_config->port_clock = link_rate; in intel_dp_compute_link_config_wide()
1991 * ->lane_count and ->port_clock set before we know in dsc_compute_link_config()
1998 pipe_config->port_clock = link_rate; in dsc_compute_link_config()
2323 pipe_config->port_clock in intel_edp_dsc_compute_pipe_bpp()
[all...]
H A Dintel_dp.h112 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
H A Dg4x_hdmi.c194 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 2, 3); in intel_hdmi_get_config()
196 dotclock = pipe_config->port_clock; in intel_hdmi_get_config()
H A Dintel_tv.c1126 tv_mode.clock = pipe_config->port_clock; in intel_tv_get_config()
1153 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); in intel_tv_get_config()
1219 pipe_config->port_clock = tv_mode->clock; in intel_tv_compute_config()
1227 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); in intel_tv_compute_config()
H A Dintel_crt.c154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_crt_get_config()
467 crtc_state->port_clock = 135000 * 2; in hsw_crt_compute_config()
H A Dintel_modeset_setup.c570 crtc_state->port_clock == 0; in has_bogus_dpll_config()
867 crtc_state->port_clock); in intel_modeset_readout_hw_state()
H A Dintel_dvo.c182 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_dvo_get_config()
H A Dintel_crtc_state_dump.c317 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src), in intel_crtc_state_dump()
H A Dintel_lvds.c153 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
H A Dintel_display.c3111 pipe_config->port_clock / pipe_config->pixel_multiplier; in i9xx_get_pipe_config()
4058 dotclock = intel_dotclock_calculate(pipe_config->port_clock, in intel_crtc_dotclock()
4061 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24, in intel_crtc_dotclock()
4064 dotclock = pipe_config->port_clock; in intel_crtc_dotclock()
4689 crtc_state->port_clock = 0; in intel_modeset_pipe_config()
4720 if (!crtc_state->port_clock) in intel_modeset_pipe_config()
4721 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
5359 PIPE_CONF_CHECK_I(port_clock); in intel_pipe_config_compare()
H A Dintel_snps_phy.c1802 if (crtc_state->port_clock == tables[i]->clock) { in intel_mpllb_calc_state()
1811 crtc_state->port_clock); in intel_mpllb_calc_state()
H A Dintel_fdi.c290 return pipe_config->port_clock; /* SPLL */ in intel_fdi_link_freq()

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