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Searched refs:idx_value (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dr200.c157 u32 idx_value; in r200_packet0_check() local
161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
189 track->zb.offset = idx_value; in r200_packet0_check()
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
202 track->cb[0].offset = idx_value; in r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
226 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
273 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()
274 ib[idx] = idx_value in r200_packet0_check()
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H A Dr300.c637 u32 idx_value; in r300_packet0_check() local
641 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
673 track->cb[i].offset = idx_value; in r300_packet0_check()
675 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
686 track->zb.offset = idx_value; in r300_packet0_check()
688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
716 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()
717 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
726 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
736 track->vap_vf_cntl = idx_value; in r300_packet0_check()
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H A Dr100.c1339 u32 idx_value; in r100_packet3_load_vbpntr() local
1359 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1362 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1374 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1385 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1388 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1591 u32 idx_value; in r100_packet0_check() local
1596 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1625 track->zb.offset = idx_value; in r100_packet0_check()
1627 ib[idx] = idx_value in r100_packet0_check()
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H A Dr600_cs.c1636 u32 idx_value; in r600_packet3_check() local
1641 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1674 (idx_value & 0xfffffff0) + in r600_packet3_check()
1715 idx_value + in r600_packet3_check()
1757 if (idx_value & 0x10) { in r600_packet3_check()
1772 } else if (idx_value & 0x100) { in r600_packet3_check()
1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()
1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()
1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()
2025 start_reg = (idx_value << in r600_packet3_check()
2382 u32 idx, idx_value; r600_dma_cs_parse() local
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H A Devergreen_cs.c1783 u32 idx_value; in evergreen_packet3_check() local
1788 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1821 (idx_value & 0xfffffff0) + in evergreen_packet3_check()
1867 idx_value + in evergreen_packet3_check()
1902 idx_value + in evergreen_packet3_check()
2013 if (idx_value != 1) { in evergreen_packet3_check()
2046 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2048 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2080 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2093 if (idx_value in evergreen_packet3_check()
3442 u32 idx_value = ib[idx]; evergreen_vm_packet3_check() local
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H A Dsi.c4464 u32 idx_value = ib[idx]; in si_vm_packet3_cp_dma_check() local
4468 start_reg = idx_value << 2; in si_vm_packet3_cp_dma_check()
4515 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local
4566 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4573 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4575 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4588 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4595 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4602 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()
4633 u32 idx_value in si_vm_packet3_compute_check() local
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