Searched refs:dtbclk (Results 1 – 10 of 10) sorted by relevance
182 min_table->max_clocks_khz.dtbclk = soc_bb->clk_table.dtbclk.clk_values_khz[soc_bb->clk_table.dtbclk.num_clk_values - 1]; in build_min_clock_table() 187 min_table->max_ss_clocks_khz.dtbclk = (unsigned int)((double)min_table->max_clocks_khz.dtbclk / (1.0 + soc_bb->dcn_downspread_percent / 100.0)); in build_min_clock_table()
214 /* dtbclk */ in override_dml_init_with_values_from_smu() 216 dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels; in override_dml_init_with_values_from_smu() 218 if (i < dml_clk_table->dtbclk.num_clk_values) { in override_dml_init_with_values_from_smu() 222 dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000; in override_dml_init_with_values_from_smu() 223 dml_clk_table->dtbclk.num_clk_values = i + 1; in override_dml_init_with_values_from_smu() 225 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu() 226 dml_clk_table->dtbclk.num_clk_values = i; in override_dml_init_with_values_from_smu() 229 dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000; in override_dml_init_with_values_from_smu() 232 dml_clk_table->dtbclk.clk_values_khz[i] = 0; in override_dml_init_with_values_from_smu()
124 struct dml2_clk_table dtbclk; member
106 .dtbclk = {
34 unsigned int dtbclk; member 43 unsigned int dtbclk; member
70 uint32_t CLK1_CLK4_CURRENT_CNT; //dtbclk80 uint32_t CLK1_CLK4_BYPASS_CNTL; //dtbclk bypass190 uint32_t dtbclk; member
384 //Get dtbclk in khz in dcn401_dump_clk_registers() 385 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn401_dump_clk_registers() 512 clk_register_dump.dtbclk, in dcn401_auto_dpm_test_log() 1481 dtb_ref_clk_khz = clk_mgr_base->boot_snapshot.dtbclk; in dcn401_get_dtb_ref_freq_khz() 1593 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn401_clk_mgr_construct() 1594 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn401_clk_mgr_construct()
933 //Get dtbclk in khz in dcn32_dump_clk_registers() 934 regs_and_bypass->dtbclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers() 1199 clk_mgr->base.clks.ref_dtbclk_khz != clk_mgr->base.boot_snapshot.dtbclk) { in dcn32_clk_mgr_construct() 1200 clk_mgr->base.clks.ref_dtbclk_khz = clk_mgr->base.boot_snapshot.dtbclk; in dcn32_clk_mgr_construct()
401 result = round_up_and_copy_to_next_dpm(mode_support_result->per_stream[i].dtbclk_khz, &display_cfg->stream_programming[i].min_clocks.dcn4x.dtbclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm() 410 result = round_up_to_next_dpm(&display_cfg->min_clocks.dcn4x.dtbrefclk_khz, &state_table->dtbclk); in map_min_clocks_to_dpm()
8707 if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_ss_clocks_khz.dtbclk / 1000)) { in dml_core_mode_support() 8714 * required - by setting phantom dtbclk to 0 we ignore it. in dml_core_mode_support()