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Searched refs:dpll_hw_state (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c74 const struct intel_dpll_hw_state *dpll_hw_state);
91 struct intel_dpll_hw_state *dpll_hw_state);
99 const struct intel_dpll_hw_state *dpll_hw_state);
118 const struct intel_dpll_hw_state *dpll_hw_state);
363 const struct intel_dpll_hw_state *dpll_hw_state, in intel_find_dpll() argument
390 if (memcmp(dpll_hw_state, in intel_find_dpll()
392 sizeof(*dpll_hw_state)) == 0) { in intel_find_dpll()
441 const struct intel_dpll_hw_state *dpll_hw_state) in intel_reference_dpll() argument
448 dpll_state[pll->index].hw_state = *dpll_hw_state; in intel_reference_dpll()
530 struct intel_dpll_hw_state *dpll_hw_state) in ibx_pch_dpll_get_hw_state() argument
566 ibx_pch_dpll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) ibx_pch_dpll_enable() argument
649 ibx_dump_hw_state(struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) ibx_dump_hw_state() argument
696 hsw_ddi_wrpll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_wrpll_enable() argument
708 hsw_ddi_spll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_spll_enable() argument
751 hsw_ddi_wrpll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_wrpll_get_hw_state() argument
773 hsw_ddi_spll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_spll_get_hw_state() argument
1000 hsw_ddi_wrpll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_wrpll_get_freq() argument
1126 hsw_ddi_lcpll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_lcpll_get_freq() argument
1178 hsw_ddi_spll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_spll_get_freq() argument
1255 hsw_dump_hw_state(struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) hsw_dump_hw_state() argument
1300 hsw_ddi_lcpll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) hsw_ddi_lcpll_get_hw_state() argument
1382 skl_ddi_pll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_pll_enable() argument
1404 skl_ddi_dpll0_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_dpll0_enable() argument
1429 skl_ddi_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_pll_get_hw_state() argument
1467 skl_ddi_dpll0_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_dpll0_get_hw_state() argument
1740 skl_ddi_wrpll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_wrpll_get_freq() argument
1888 skl_ddi_lcpll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_lcpll_get_freq() argument
1967 skl_ddi_pll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) skl_ddi_pll_get_freq() argument
1988 skl_dump_hw_state(struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) skl_dump_hw_state() argument
2042 bxt_ddi_pll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) bxt_ddi_pll_enable() argument
2164 bxt_ddi_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) bxt_ddi_pll_get_hw_state() argument
2364 bxt_ddi_pll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) bxt_ddi_pll_get_freq() argument
2458 bxt_dump_hw_state(struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) bxt_dump_hw_state() argument
2759 icl_ddi_tbt_pll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) icl_ddi_tbt_pll_get_freq() argument
2830 icl_ddi_combo_pll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) icl_ddi_combo_pll_get_freq() argument
2892 icl_calc_dpll_state(struct intel_display * display,const struct skl_wrpll_params * pll_params,struct intel_dpll_hw_state * dpll_hw_state) icl_calc_dpll_state() argument
2998 icl_calc_mg_pll_state(struct intel_crtc_state * crtc_state,struct intel_dpll_hw_state * dpll_hw_state) icl_calc_mg_pll_state() argument
3203 icl_ddi_mg_pll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) icl_ddi_mg_pll_get_freq() argument
3542 mg_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) mg_pll_get_hw_state() argument
3609 dkl_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) dkl_pll_get_hw_state() argument
3681 icl_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state,i915_reg_t enable_reg) icl_pll_get_hw_state() argument
3742 combo_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) combo_pll_get_hw_state() argument
3751 tbt_pll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) tbt_pll_get_hw_state() argument
3958 combo_pll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) combo_pll_enable() argument
3982 tbt_pll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) tbt_pll_enable() argument
4003 mg_pll_enable(struct intel_display * display,struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) mg_pll_enable() argument
4086 icl_dump_hw_state(struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) icl_dump_hw_state() argument
4485 intel_dpll_get_freq(struct intel_display * display,const struct intel_dpll * pll,const struct intel_dpll_hw_state * dpll_hw_state) intel_dpll_get_freq() argument
4503 intel_dpll_get_hw_state(struct intel_display * display,struct intel_dpll * pll,struct intel_dpll_hw_state * dpll_hw_state) intel_dpll_get_hw_state() argument
4587 intel_dpll_dump_hw_state(struct intel_display * display,struct drm_printer * p,const struct intel_dpll_hw_state * dpll_hw_state) intel_dpll_dump_hw_state() argument
4629 struct intel_dpll_hw_state dpll_hw_state = {}; verify_single_dpll_state() local
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H A Dintel_dpll_mgr.h417 const struct intel_dpll_hw_state *dpll_hw_state);
420 struct intel_dpll_hw_state *dpll_hw_state);
431 const struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_dpll.c378 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_pll_refclk()
391 struct intel_dpll_hw_state *dpll_hw_state) in i9xx_dpll_get_hw_state() argument
394 struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx; in i9xx_dpll_get_hw_state()
427 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_crtc_clock_get()
521 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in vlv_crtc_clock_get()
549 const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in chv_crtc_clock_get()
1076 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i9xx_compute_dpll()
1143 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; in i8xx_compute_dpll()
1228 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_crtc_compute_clock()
1342 struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state in ilk_compute_dpll()
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H A Dintel_dpll.h27 struct intel_dpll_hw_state *dpll_hw_state);
H A Dintel_cx0_phy.c2093 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2099 intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10, in intel_c10pll_calc_state()
2102 &crtc_state->dpll_hw_state.cx0pll); in intel_c10pll_calc_state()
2103 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()
2241 struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_compute_hdmi_tmds_pll()
2355 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2357 &crtc_state->dpll_hw_state.cx0pll, in intel_c20pll_calc_state()
2359 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()
3096 __intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll, in intel_cx0pll_enable()
3424 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state in intel_c10pll_state_verify()
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H A Dintel_pch_display.c536 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
539 tmp = crtc_state->dpll_hw_state.i9xx.dpll; in ilk_pch_get_config()
H A Dintel_snps_phy.c1803 crtc_state->dpll_hw_state.mpllb = *tables[i]; in intel_mpllb_calc_state()
1810 intel_snps_hdmi_pll_compute_mpllb(&crtc_state->dpll_hw_state.mpllb, in intel_mpllb_calc_state()
1823 const struct intel_mpllb_state *pll_state = &crtc_state->dpll_hw_state.mpllb; in intel_mpllb_enable()
1988 const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->dpll_hw_state.mpllb; in intel_mpllb_state_verify()
H A Dintel_crtc_state_dump.c345 intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
H A Dintel_ddi.c4237 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4243 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4245 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4248 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4256 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4257 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4350 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
H A Dintel_display.c1331 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
3078 i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state); in i9xx_get_pipe_config()
3081 tmp = pipe_config->dpll_hw_state.i9xx.dpll_md; in i9xx_get_pipe_config()
3087 tmp = pipe_config->dpll_hw_state.i9xx.dpll; in i9xx_get_pipe_config()
4586 saved_state->dpll_hw_state = crtc_state->dpll_hw_state; in intel_crtc_prepare_cleared_state()
5343 PIPE_CONF_CHECK_PLL(dpll_hw_state); in intel_pipe_config_compare()
5347 PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); in intel_pipe_config_compare()
H A Dintel_display_types.h1092 struct intel_dpll_hw_state dpll_hw_state; member
1096 * setting shared_dpll and dpll_hw_state to one of these reserved ones.