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Searched refs:dp_m_n (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_mst.c346 &crtc_state->dp_m_n); in intel_dp_mtp_tu_compute_config()
367 * crtc_state->dp_m_n.tu), provided that the driver doesn't in intel_dp_mtp_tu_compute_config()
393 drm_WARN_ON(display->drm, remote_tu < crtc_state->dp_m_n.tu); in intel_dp_mtp_tu_compute_config()
394 crtc_state->dp_m_n.tu = remote_tu; in intel_dp_mtp_tu_compute_config()
405 crtc_state->dp_m_n.tu = ALIGN(crtc_state->dp_m_n.tu, in intel_dp_mtp_tu_compute_config()
408 if (crtc_state->dp_m_n.tu <= 64) in intel_dp_mtp_tu_compute_config()
409 slots = crtc_state->dp_m_n.tu; in intel_dp_mtp_tu_compute_config()
418 drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu); in intel_dp_mtp_tu_compute_config()
718 pipe_config->dp_m_n in mst_stream_compute_config()
[all...]
H A Dintel_drrs.c169 crtc->drrs.m_n = crtc_state->dp_m_n; in intel_drrs_activate()
H A Dg4x_dp.c326 intel_pch_transcoder_get_m1_n1(crtc, &crtc_state->dp_m_n); in g4x_dp_get_m_n()
330 &crtc_state->dp_m_n); in g4x_dp_get_m_n()
403 &pipe_config->dp_m_n); in intel_dp_get_config()
H A Dintel_crtc_state_dump.c236 &pipe_config->dp_m_n); in intel_crtc_state_dump()
H A Dintel_pch_display.c407 intel_pch_transcoder_set_m1_n1(crtc, &crtc_state->dp_m_n); in ilk_pch_enable()
H A Dintel_display.c1100 * dp_m_n vs. dp_m2_n2 confusion on BDW+. in intel_post_plane_update_after_readout()
1502 &crtc_state->dp_m_n); in ilk_configure_cpu_transcoder()
1633 &crtc_state->dp_m_n); in hsw_configure_cpu_transcoder()
2021 &crtc_state->dp_m_n); in i9xx_configure_cpu_transcoder()
4059 &pipe_config->dp_m_n); in intel_crtc_dotclock()
5249 PIPE_CONF_CHECK_M_N(dp_m_n); in intel_pipe_config_compare()
5251 PIPE_CONF_CHECK_M_N(dp_m_n); in intel_pipe_config_compare()
5742 if (intel_compare_link_m_n(&old_crtc_state->dp_m_n, in intel_crtc_check_fastset()
5743 &new_crtc_state->dp_m_n)) in intel_crtc_check_fastset()
6607 &new_crtc_state->dp_m_n); in intel_pipe_fastset()
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H A Dintel_ddi.c2729 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in mtl_ddi_pre_enable_dp()
2876 ret = drm_dp_dpcd_write_payload(&intel_dp->aux, 1, 0, crtc_state->dp_m_n.tu); in tgl_ddi_pre_enable_dp()
4049 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_sst()
4085 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, &crtc_state->dp_m_n); in intel_ddi_read_func_ctl_dp_mst()
4505 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
H A Dintel_display_types.h1111 struct intel_link_m_n dp_m_n; member
H A Dintel_dp.c3286 &pipe_config->dp_m_n); in intel_dp_compute_config()
3295 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count; in intel_dp_compute_config()