| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 125 .dispclk_mhz = 1200.0,
134 .dispclk_mhz = 1200.0,
143 .dispclk_mhz = 1200.0,
152 .dispclk_mhz = 1200.0,
161 .dispclk_mhz = 1200.0,
369 .dispclk_mhz = 556.0,
378 .dispclk_mhz = 625.0,
387 .dispclk_mhz = 625.0,
396 .dispclk_mhz = 1112.0,
405 .dispclk_mhz
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 122 .dispclk_mhz = 1015.0,
134 .dispclk_mhz = 1015.0,
146 .dispclk_mhz = 1015.0,
158 .dispclk_mhz = 1015.0,
170 .dispclk_mhz = 1015.0,
356 s[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn301_fpu_update_bw_bounding_box()
457 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_fpu_calculate_wm_and_dlg()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_fpu_calculate_wm_and_dlg()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn351/ |
| H A D | dcn351_fpu.c | 105 .dispclk_mhz = 600.0,
118 .dispclk_mhz = 800.0,
131 .dispclk_mhz = 800.0,
144 .dispclk_mhz = 960.0,
157 .dispclk_mhz = 1066.7,
170 .dispclk_mhz = 1200.0,
183 .dispclk_mhz = 1371.4,
196 .dispclk_mhz = 1600.0,
282 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn351_update_bw_bounding_box_fpu()
283 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn351_update_bw_bounding_box_fpu()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 106 .dispclk_mhz = 1200.0,
115 .dispclk_mhz = 1200.0,
124 .dispclk_mhz = 1200.0,
133 .dispclk_mhz = 1200.0,
142 .dispclk_mhz = 1200.0,
209 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn314_update_bw_bounding_box_fpu()
210 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn314_update_bw_bounding_box_fpu()
244 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz : in dcn314_update_bw_bounding_box_fpu()
245 dcn3_14_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn314_update_bw_bounding_box_fpu()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 122 .dispclk_mhz = 1200.0,
131 .dispclk_mhz = 1200.0,
140 .dispclk_mhz = 1200.0,
149 .dispclk_mhz = 1200.0,
158 .dispclk_mhz = 1200.0,
248 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn35_update_bw_bounding_box_fpu()
249 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn35_update_bw_bounding_box_fpu()
293 clock_limits[i].dispclk_mhz = max_dispclk_mhz ? in dcn35_update_bw_bounding_box_fpu()
295 dcn3_5_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn35_update_bw_bounding_box_fpu()
362 dc->dml2_options.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz in dcn35_update_bw_bounding_box_fpu()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 228 .dispclk_mhz = 513.0,
239 .dispclk_mhz = 642.0,
250 .dispclk_mhz = 734.0,
261 .dispclk_mhz = 1100.0,
272 .dispclk_mhz = 1284.0,
284 .dispclk_mhz = 1284.0,
339 .dispclk_mhz = 513.0,
350 .dispclk_mhz = 642.0,
361 .dispclk_mhz = 734.0,
372 .dispclk_mhz
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 117 .dispclk_mhz = 562.0,
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
236 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
325 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 116 .dispclk_mhz = 562.0,
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
232 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
331 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 261 .dispclk_mhz = 640,
269 .dispclk_mhz = 739,
277 .dispclk_mhz = 960,
285 .dispclk_mhz = 1200,
293 .dispclk_mhz = 1372,
518 bw_params->clk_table.entries[i].dispclk_mhz = clock_table->DispClocks[i]; in dcn315_clk_mgr_helper_populate_bw_params()
534 bw_params->clk_table.entries[i-1].dispclk_mhz = clock_table->DispClocks[clock_table->NumDispClkLevelsEnabled - 1]; in dcn315_clk_mgr_helper_populate_bw_params()
552 if (!bw_params->clk_table.entries[i].dispclk_mhz) in dcn315_clk_mgr_helper_populate_bw_params()
553 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 129 .dispclk_mhz = 562.0,
482 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn30_fpu_calculate_wm_and_dlg()
486 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
489 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
490 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
537 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_update_max_clk()
588 dcn3_0_soc.clock_limits[i].dispclk_mhz = dcn30_bb_max_clk->max_dispclk_mhz; in dcn30_fpu_update_bw_bounding_box()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 132 .dispclk_mhz = 2150.0,
1782 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz in dcn32_calculate_dlg_params()
2599 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt); in dcn32_calculate_wm_and_dlg_fpu()
2603 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn32_calculate_wm_and_dlg_fpu()
2606 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn32_calculate_wm_and_dlg_fpu()
2607 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn32_calculate_wm_and_dlg_fpu()
2683 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn32_patch_dpm_table()
2684 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn32_patch_dpm_table()
2702 bw_params->clk_table.entries[0].dispclk_mhz in dcn32_patch_dpm_table()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 213 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn32_init_clocks()
216 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK); in dcn32_init_clocks()
218 if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950) in dcn32_init_clocks()
219 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950; in dcn32_init_clocks()
238 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
240 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
244 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) in dcn32_init_clocks()
245 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; in dcn32_init_clocks()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_policy.c | 145 if (p->in_states->state_array[i].dispclk_mhz > max_dispclk_mhz) in dml2_policy_build_synthetic_soc_states()
146 max_dispclk_mhz = (int) p->in_states->state_array[i].dispclk_mhz; in dml2_policy_build_synthetic_soc_states()
167 s->entry.dispclk_mhz = max_dispclk_mhz; in dml2_policy_build_synthetic_soc_states()
|
| H A D | dml2_translation_helper.c | 367 p->in_states->state_array[0].dispclk_mhz = 2150.0; in dml2_init_soc_states()
403 p->in_states->state_array[0].dispclk_mhz = 1720.0; in dml2_init_soc_states()
438 p->in_states->state_array[0].dispclk_mhz = 2000; //2150.0; in dml2_init_soc_states()
552 p->in_states->state_array[i].dispclk_mhz = in dml2_init_soc_states()
553 dml2->config.bbox_overrides.clks_table.clk_entries[i].dispclk_mhz; in dml2_init_soc_states()
574 if (p->in_states->state_array[i].dispclk_mhz > max_dispclk_mhz) in dml2_init_soc_states()
575 max_dispclk_mhz = (int)p->in_states->state_array[i].dispclk_mhz; in dml2_init_soc_states()
588 p->out_states->state_array[i].dispclk_mhz = max_dispclk_mhz; in dml2_init_soc_states()
720 out->state_array[i].dispclk_mhz = dc->dml.soc.clock_limits[i].dispclk_mhz; in dml2_translate_soc_states()
[all...] |
| H A D | dml2_wrapper.h | 162 unsigned int dispclk_mhz; member
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_socbb.h | 33 uint32_t dispclk_mhz; member
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 677 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn314_clk_mgr_helper_populate_bw_params()
693 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn314_clk_mgr_helper_populate_bw_params()
703 bw_params->clk_table.entries[i].dispclk_mhz = find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS); in dcn314_clk_mgr_helper_populate_bw_params()
724 if (!bw_params->clk_table.entries[i].dispclk_mhz) in dcn314_clk_mgr_helper_populate_bw_params()
725 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 274 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn401_init_clocks()
276 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DISPCLK); in dcn401_init_clocks()
277 if (num_entries_per_clk->num_dispclk_levels && clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz == in dcn401_init_clocks()
278 clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_dispclk_levels - 1].dispclk_mhz) in dcn401_init_clocks()
279 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 0; in dcn401_init_clocks()
293 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn401_init_clocks()
295 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn401_init_clocks()
322 clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz) || in dcn401_is_dc_mode_present()
1513 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 : in dcn401_get_max_clock_khz()
1523 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 100 in dcn401_get_max_clock_khz()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_structs.h | 165 double dispclk_mhz; member
552 double dispclk_mhz; member
|
| H A D | display_mode_lib.c | 280 dml_print("DML PARAMS: dispclk_mhz = %3.2f\n", clks_cfg->dispclk_mhz); in dml_log_pipe_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/ |
| H A D | dcn201_resource.c | 145 .dispclk_mhz = 300.0,
156 .dispclk_mhz = 1200.0,
167 .dispclk_mhz = 1200.0,
178 .dispclk_mhz = 1200.0,
190 .dispclk_mhz = 1200.0,
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_translation_helper.c | 173 if (config->use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz && in override_dml_init_with_values_from_smu()
174 dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) { in override_dml_init_with_values_from_smu()
175 if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) { in override_dml_init_with_values_from_smu()
176 dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000; in override_dml_init_with_values_from_smu()
183 dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000; in override_dml_init_with_values_from_smu()
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 979 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn35_clk_mgr_helper_populate_bw_params()
1000 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk; in dcn35_clk_mgr_helper_populate_bw_params()
1011 bw_params->clk_table.entries[i].dispclk_mhz = in dcn35_clk_mgr_helper_populate_bw_params()
1042 if (!bw_params->clk_table.entries[i].dispclk_mhz) in dcn35_clk_mgr_helper_populate_bw_params()
1043 bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz; in dcn35_clk_mgr_helper_populate_bw_params()
|
| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| H A D | dml_top_display_cfg_types.h | 463 double dispclk_mhz; member
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 122 unsigned int dispclk_mhz; member
|