| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_reg_sr.c | 54 * Don't allow overwriting values: clr_bits/set_bits should be disjoint in compatible_entries()
57 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits || in compatible_entries()
58 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits) in compatible_entries()
88 pentry->clr_bits |= e->clr_bits; in xe_reg_sr_add()
111 idx, e->clr_bits, e->set_bits, in xe_reg_sr_add()
137 * Set them to clr_bits since that is always a superset of the bits in apply_one_mmio()
144 val = entry->clr_bits << 1 in apply_one_mmio()
[all...] |
| H A D | xe_rtp.h | 244 .clr_bits = ~0u, .set_bits = (val_), \
262 .clr_bits = val_, .set_bits = val_, \
280 .clr_bits = val_, .set_bits = 0, \
297 .clr_bits = mask_bits_, .set_bits = val_, \
302 .clr_bits = (mask_bits_), .set_bits = (val_), \
318 .clr_bits = RING_FORCE_TO_NONPRIV_MASK_VALID, \
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| H A D | xe_reg_sr_types.h | 16 u32 clr_bits; member
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| H A D | xe_gt.c | 201 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
241 val = entry->clr_bits << 16; in emit_wa_job()
242 else if (entry->clr_bits == ~0) in emit_wa_job()
259 if (entry->reg.masked || entry->clr_bits == ~0) in emit_wa_job()
269 *cs++ = entry->clr_bits; in emit_wa_job()
288 entry->reg.addr, entry->clr_bits, entry->set_bits); in emit_wa_job()
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| H A D | xe_rtp_types.h | 26 * @clr_bits: bits to clear when updating register. It's always a
29 u32 clr_bits; member
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| H A D | xe_rtp.c | 177 .clr_bits = action->clr_bits, in rtp_add_sr_entry()
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| H A D | xe_reg_whitelist.c | 109 .clr_bits = ~0u, in whitelist_apply_to_hwe()
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| /linux/drivers/gpu/drm/sprd/ |
| H A D | sprd_dpu.h | 83 dpu_reg_clr(struct dpu_context *ctx, u32 offset, u32 clr_bits) in dpu_reg_clr() argument
87 writel(bits & ~clr_bits, ctx->base + offset); in dpu_reg_clr()
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| /linux/drivers/tty/serial/ |
| H A D | rp2.c | 233 u32 clr_bits, u32 set_bits) in rp2_rmw() argument
236 tmp &= ~clr_bits; in rp2_rmw()
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| /linux/drivers/gpu/drm/xe/tests/ |
| H A D | xe_rtp_test.c | 336 KUNIT_EXPECT_EQ(test, sr_entry->clr_bits, param->expected_clr_bits); in xe_rtp_process_to_sr_tests()
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| /linux/drivers/media/platform/qcom/camss/ |
| H A D | camss-vfe-4-1.c | 221 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
225 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
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| H A D | camss-vfe-4-8.c | 248 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
252 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
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| H A D | camss-vfe-4-7.c | 265 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) in vfe_reg_clr() argument
269 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_ddi.c | 3060 u32 clr_bits, wait_bits; in mtl_ddi_disable_d2d() local
3067 clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3071 clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE; in mtl_ddi_disable_d2d()
3075 intel_de_rmw(display, reg, clr_bits, 0); in mtl_ddi_disable_d2d()
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