Searched refs:clk_csr (Results 1 – 11 of 11) sorted by relevance
100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read() 183 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write() 289 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c22() 329 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read_c45() 389 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c22() 430 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write_c45()
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data() 77 plat->clk_csr = 5; in snps_gmac5_default_data()
321 * If a specific clk_csr value is passed from the platform333 /* Platform provided default clk_csr would be assumed valid in stmmac_clk_csr_set() 340 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set() 342 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set() 344 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set() 346 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set() 348 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set() 350 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set() 352 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set() 354 priv->clk_csr in stmmac_clk_csr_set() [all...]
293 int clk_csr; member
93 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
46 int clk_csr; member
176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set() 178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set() 180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set() 182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set() 184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set() 186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set() 2157 /* If a specific clk_csr value is passed from the platform in sxgbe_drv_probe() 2163 if (!priv->plat->clk_csr) in sxgbe_drv_probe() 2166 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe() [all...]
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
489 int clk_csr; member
475 unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr; in qat_hal_clr_reset() local 494 csr_val = GET_CAP_CSR(handle, clk_csr); in qat_hal_clr_reset() 496 SET_CAP_CSR(handle, clk_csr, csr_val); in qat_hal_clr_reset()
370 int clk_csr;