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/linux/include/linux/
H A Dsizes.h54 #define SZ_4G _AC(0x100000000, ULL)
55 #define SZ_8G _AC(0x200000000, ULL)
56 #define SZ_16G _AC(0x400000000, ULL)
57 #define SZ_32G _AC(0x800000000, ULL)
58 #define SZ_64G _AC(0x1000000000, ULL)
59 #define SZ_128G _AC(0x2000000000, ULL)
60 #define SZ_256G _AC(0x4000000000, ULL)
61 #define SZ_512G _AC(0x8000000000, ULL)
63 #define SZ_1T _AC(0x10000000000, ULL)
64 #define SZ_2T _AC(0x20000000000, ULL)
[all...]
H A Dbitfield.h76 (1ULL << __bf_shf(_mask))); \
88 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \
101 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \
115 __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
140 __BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + \
/linux/arch/parisc/include/asm/
H A Dpdc_chassis.h58 #define PDC_CHASSIS_LED_RUN_OFF (0ULL << 4)
59 #define PDC_CHASSIS_LED_RUN_FLASH (1ULL << 4)
60 #define PDC_CHASSIS_LED_RUN_ON (2ULL << 4)
61 #define PDC_CHASSIS_LED_RUN_NC (3ULL << 4)
62 #define PDC_CHASSIS_LED_ATTN_OFF (0ULL << 6)
63 #define PDC_CHASSIS_LED_ATTN_FLASH (1ULL << 6)
64 #define PDC_CHASSIS_LED_ATTN_NC (3ULL << 6) /* ATTN ON is invalid */
65 #define PDC_CHASSIS_LED_FAULT_OFF (0ULL << 8)
66 #define PDC_CHASSIS_LED_FAULT_FLASH (1ULL << 8)
67 #define PDC_CHASSIS_LED_FAULT_ON (2ULL <<
[all...]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-address.h295 #define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
300 #define CVMX_OCT_DID_MIS 0ULL /* misc stuff */
301 #define CVMX_OCT_DID_GMX0 1ULL
302 #define CVMX_OCT_DID_GMX1 2ULL
303 #define CVMX_OCT_DID_PCI 3ULL
304 #define CVMX_OCT_DID_KEY 4ULL
305 #define CVMX_OCT_DID_FPA 5ULL
306 #define CVMX_OCT_DID_DFA 6ULL
307 #define CVMX_OCT_DID_ZIP 7ULL
308 #define CVMX_OCT_DID_RNG 8ULL
[all...]
/linux/arch/x86/include/asm/
H A Dsegment.h14 ((((base) & _AC(0xff000000,ULL)) << (56-24)) | \
15 (((flags) & _AC(0x0000f0ff,ULL)) << 40) | \
16 (((limit) & _AC(0x000f0000,ULL)) << (48-16)) | \
17 (((base) & _AC(0x00ffffff,ULL)) << 16) | \
18 (((limit) & _AC(0x0000ffff,ULL))))
H A Dpgtable-3level.h105 return pxx_xchg64(pte, ptep, 0ULL); in native_ptep_get_and_clear()
110 return pxx_xchg64(pmd, pmdp, 0ULL); in native_pmdp_get_and_clear()
115 return pxx_xchg64(pud, pudp, 0ULL); in native_pudp_get_and_clear()
H A Dmem_encrypt.h71 #define sme_me_mask 0ULL
72 #define sev_status 0ULL
/linux/include/asm-generic/
H A Ddiv64.h84 ___m = (~0ULL / ___b) * ___p; \
85 ___m += (((~0ULL % ___b + 1) * ___p) + ___b - 1) / ___b; \
88 ___x = ~0ULL / ___b * ___b - 1; \
109 ___m = (~0ULL / ___b) * ___p; \
110 ___m += ((~0ULL % ___b + 1) * ___p) / ___b; \
/linux/tools/include/linux/
H A Dbitfield.h72 (1ULL << __bf_shf(_mask))); \
84 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \
97 __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \
111 __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_devlink.c75 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_intr_handler()
110 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_gen_handler()
145 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_err_handler()
180 rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL); in rvu_nix_af_rvu_ras_handler()
199 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
200 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
201 rvu_write64(rvu, blkaddr, NIX_AF_ERR_INT_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
202 rvu_write64(rvu, blkaddr, NIX_AF_RAS_ENA_W1C, ~0ULL); in rvu_nix_unregister_interrupts()
240 rvu_write64(rvu, blkaddr, NIX_AF_RVU_INT_ENA_W1S, ~0ULL); in rvu_nix_register_interrupts()
248 rvu_write64(rvu, blkaddr, NIX_AF_GEN_INT_ENA_W1S, ~0ULL); in rvu_nix_register_interrupts()
[all...]
/linux/drivers/of/
H A Dof_test.c127 .start = ULL(0x100000000),
130 .res_start = ULL(0x100000000),
131 .res_end = ULL(0x100000000),
138 .res_end = ULL(0x100000ffe),
/linux/tools/perf/Documentation/
H A Dperf-dlfilter.txt231 PERF_DLFILTER_FLAG_BRANCH = 1ULL << 0,
232 PERF_DLFILTER_FLAG_CALL = 1ULL << 1,
233 PERF_DLFILTER_FLAG_RETURN = 1ULL << 2,
234 PERF_DLFILTER_FLAG_CONDITIONAL = 1ULL << 3,
235 PERF_DLFILTER_FLAG_SYSCALLRET = 1ULL << 4,
236 PERF_DLFILTER_FLAG_ASYNC = 1ULL << 5,
237 PERF_DLFILTER_FLAG_INTERRUPT = 1ULL << 6,
238 PERF_DLFILTER_FLAG_TX_ABORT = 1ULL << 7,
239 PERF_DLFILTER_FLAG_TRACE_BEGIN = 1ULL << 8,
240 PERF_DLFILTER_FLAG_TRACE_END = 1ULL <<
[all...]
/linux/drivers/spi/
H A Dspi-fsi.c134 *value = 0ULL; in fsi_spi_read_reg()
233 *out = 0ULL; in fsi_spi_data_out()
257 return fsi_spi_write_reg(ctx, SPI_FSI_STATUS, 0ULL); in fsi_spi_reset()
295 seq->data = 0ULL; in fsi_spi_sequence_init()
304 u64 status = 0ULL; in fsi_spi_transfer_data()
309 u64 out = 0ULL; in fsi_spi_transfer_data()
335 u64 in = 0ULL; in fsi_spi_transfer_data()
369 u64 clock_cfg = 0ULL; in fsi_spi_transfer_init()
370 u64 status = 0ULL; in fsi_spi_transfer_init()
405 rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, 0ULL); in fsi_spi_transfer_init()
[all...]
/linux/drivers/md/bcache/
H A Dbcache_ondisk.h13 { return (k->field >> offset) & ~(~0ULL << size); } \
17 k->field &= ~(~(~0ULL << size) << offset); \
18 k->field |= (v & ~(~0ULL << size)) << offset; \
34 { return (k->ptr[i] >> offset) & ~(~0ULL << size); } \
38 k->ptr[i] &= ~(~(~0ULL << size) << offset); \
39 k->ptr[i] |= (v & ~(~0ULL << size)) << offset; \
73 .high = (1ULL << 63) | ((__u64) (size) << 20) | (inode), \
80 #define MAX_KEY_OFFSET (~0ULL >> 1)
/linux/include/vdso/
H A Dlimits.h14 #define LLONG_MAX ((long long)(~0ULL >> 1))
16 #define ULLONG_MAX (~0ULL)
/linux/drivers/block/drbd/
H A Ddrbd_vli.h141 *out = ((in & ((~0ULL) >> (64-t))) >> b) + adj; \ in vli_decode_bits()
144 adj += 1ULL << (t - b); \ in vli_decode_bits()
165 max += 1ULL << (t - b); \ in __vli_encode_bits()
261 val &= ~0ULL >> (64 - bits); in bitstream_put_bits()
312 val &= ~0ULL >> (64 - bits); in bitstream_get_bits()
/linux/fs/bcachefs/
H A Dbkey.c19 u64 v = *p & (~0ULL >> high_bit_offset); in bch2_bkey_packed_to_binary_text()
393 v = ~(~0ULL << bits); in set_inc_field_lossy()
423 u64 mask = (~0ULL >> (64 - bits)) << offset; in bkey_packed_successor()
426 *p += 1ULL << offset; in bkey_packed_successor()
444 u64 unpacked_max = ~((~0ULL << 1) << (unpacked_bits - 1)); in bkey_format_has_too_big_fields()
446 ? ~((~0ULL << 1) << (f->bits_per_field[i] - 1)) in bkey_format_has_too_big_fields()
574 u64 unpacked_max = ~((~0ULL << 1) << (unpacked_bits - 1)); in set_format_field()
578 offset = bits == unpacked_bits ? 0 : min(offset, unpacked_max - ((1ULL << bits) - 1)); in set_format_field()
656 u64 unpacked_max = ~((~0ULL << 1) << (unpacked_bits - 1)); in bch2_bkey_format_invalid()
659 ? ~((~0ULL << in bch2_bkey_format_invalid()
[all...]
H A Dbkey_cmp.h62 l_v = *l & (~0ULL >> high_bit_offset); in __bkey_cmp_bits()
63 r_v = *r & (~0ULL >> high_bit_offset); in __bkey_cmp_bits()
/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c83 u64 val = ULL(0); in cn93_vf_reset_iq()
108 u64 val = ULL(0); in cn93_vf_reset_oq()
203 u64 oq_ctl = ULL(0); in octep_vf_setup_oq_regs_cn93()
383 reg_val |= ULL(1); in octep_vf_enable_iq_cn93()
399 reg_val |= ULL(1); in octep_vf_enable_oq_cn93()
420 reg_val &= ~ULL(1); in octep_vf_disable_iq_cn93()
430 reg_val &= ~ULL(1); in octep_vf_disable_oq_cn93()
H A Doctep_vf_cnxk.c86 u64 val = ULL(0); in cnxk_vf_reset_iq()
110 u64 val = ULL(0); in cnxk_vf_reset_oq()
206 u64 oq_ctl = ULL(0); in octep_vf_setup_oq_regs_cnxk()
394 reg_val |= ULL(1); in octep_vf_enable_iq_cnxk()
410 reg_val |= ULL(1); in octep_vf_enable_oq_cnxk()
431 reg_val &= ~ULL(1); in octep_vf_disable_iq_cnxk()
441 reg_val &= ~ULL(1); in octep_vf_disable_oq_cnxk()
/linux/drivers/iommu/intel/
H A Dprq.c329 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_enable_prq()
330 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_enable_prq()
352 dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL); in intel_iommu_finish_prq()
353 dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL); in intel_iommu_finish_prq()
354 dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL); in intel_iommu_finish_prq()
/linux/fs/btrfs/
H A Dfs.h64 #define BTRFS_OLDEST_GENERATION 0ULL
213 BTRFS_MOUNT_NODATASUM = (1ULL << 0),
214 BTRFS_MOUNT_NODATACOW = (1ULL << 1),
215 BTRFS_MOUNT_NOBARRIER = (1ULL << 2),
216 BTRFS_MOUNT_SSD = (1ULL << 3),
217 BTRFS_MOUNT_DEGRADED = (1ULL << 4),
218 BTRFS_MOUNT_COMPRESS = (1ULL << 5),
219 BTRFS_MOUNT_NOTREELOG = (1ULL << 6),
220 BTRFS_MOUNT_FLUSHONCOMMIT = (1ULL << 7),
221 BTRFS_MOUNT_SSD_SPREAD = (1ULL <<
[all...]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnicvf_queues.h34 #define RBDR_SIZE0 0ULL /* 8K entries */
35 #define RBDR_SIZE1 1ULL /* 16K entries */
36 #define RBDR_SIZE2 2ULL /* 32K entries */
37 #define RBDR_SIZE3 3ULL /* 64K entries */
38 #define RBDR_SIZE4 4ULL /* 126K entries */
39 #define RBDR_SIZE5 5ULL /* 256K entries */
40 #define RBDR_SIZE6 6ULL /* 512K entries */
42 #define SND_QUEUE_SIZE0 0ULL /* 1K entries */
43 #define SND_QUEUE_SIZE1 1ULL /* 2K entries */
44 #define SND_QUEUE_SIZE2 2ULL /*
[all...]
/linux/tools/perf/bench/
H A Dmem-functions.c240 u64 cycle_start = 0ULL, cycle_end = 0ULL; in do_memcpy_cycles()
306 u64 cycle_start = 0ULL, cycle_end = 0ULL; in do_memset_cycles()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dvmmgh100.c100 VMM_WO128(pt, vmm, ptei++ * NV_MMU_VER3_DUAL_PDE__SIZE, data, 0ULL); in gh100_vmm_pd0_pte()
160 VMM_FO128(pt, vmm, pdei * NV_MMU_VER3_DUAL_PDE__SIZE, data, 0ULL, pdes); in gh100_vmm_pd0_sparse()
167 VMM_FO128(pt, vmm, pdei * NV_MMU_VER3_DUAL_PDE__SIZE, 0ULL, 0ULL, pdes); in gh100_vmm_pd0_unmap()
233 map->next = 1ULL << page->shift; in gh100_vmm_valid()

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