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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c595 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v4_0_5_disable_static_power_gating()
599 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
604 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
609 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
615 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
619 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
623 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
627 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
661 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
666 SOC15_WAIT_ON_RREG(VC in vcn_v4_0_5_enable_static_power_gating()
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H A Dvcn_v5_0_0.c559 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
564 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
570 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
576 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
582 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
587 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
592 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
597 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
633 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
639 SOC15_WAIT_ON_RREG(VC in vcn_v5_0_0_enable_static_power_gating()
[all...]
H A Dvcn_v1_0.c764 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); in vcn_1_0_disable_static_power_gating()
778 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); in vcn_1_0_disable_static_power_gating()
829 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); in vcn_1_0_enable_static_power_gating()
1190 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1196 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1205 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1250 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1253 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1256 SOC15_WAIT_ON_RREG(UV in vcn_v1_0_stop_dpg_mode()
[all...]
H A Dvcn_v3_0.c704 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
722 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
777 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v3_0_enable_static_power_gating()
828 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
1608 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1613 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1616 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1619 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1621 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1652 r = SOC15_WAIT_ON_RREG(VC in vcn_v3_0_stop()
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H A Dvcn_v2_0.c790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
804 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); in vcn_v2_0_disable_static_power_gating()
858 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); in vcn_v2_0_enable_static_power_gating()
1191 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1196 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1199 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1202 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1204 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1233 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1241 r = SOC15_WAIT_ON_RREG(VC in vcn_v2_0_stop()
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H A Dvcn_v4_0.c653 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, in vcn_v4_0_disable_static_power_gating()
675 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF); in vcn_v4_0_disable_static_power_gating()
739 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v4_0_enable_static_power_gating()
791 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_disable_clock_gating()
1584 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1589 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_stop_dpg_mode()
1591 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1632 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_stop()
1640 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); in vcn_v4_0_stop()
1650 r = SOC15_WAIT_ON_RREG(VC in vcn_v4_0_stop()
[all...]
H A Dvcn_v2_5.c824 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
1575 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1580 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1583 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1586 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1588 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1619 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1627 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1638 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1694 ret_code = SOC15_WAIT_ON_RREG(VC in vcn_v2_5_pause_dpg_mode()
[all...]
H A Djpeg_v3_0.c296 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v3_0_disable_static_power_gating()
331 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v3_0_enable_static_power_gating()
492 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, in jpeg_v3_0_wait_for_idle()
H A Djpeg_v4_0_5.c379 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_disable_static_power_gating()
404 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_enable_static_power_gating()
435 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
677 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS, in jpeg_v4_0_5_wait_for_idle()
H A Dumsch_mm_v4_0.c67 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_load_microcode()
164 r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF); in umsch_mm_v4_0_load_microcode()
261 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_ring_stop()
H A Djpeg_v5_0_0.c275 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, in jpeg_v5_0_0_disable_power_gating()
295 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v5_0_0_enable_power_gating()
578 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v5_0_0_wait_for_idle()
H A Dvcn_v5_0_1.c576 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, in vcn_v5_0_1_pause_dpg_mode()
1074 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v5_0_1_stop_dpg_mode()
1079 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v5_0_1_stop_dpg_mode()
1117 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_1_stop()
1125 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
1135 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
1312 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_1_wait_for_idle()
H A Djpeg_v4_0.c333 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v4_0_disable_static_power_gating()
368 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, in jpeg_v4_0_enable_static_power_gating()
652 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v4_0_wait_for_idle()
H A Djpeg_v2_0.c239 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
270 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
700 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
H A Dvcn_v4_0_3.c680 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_3_disable_clock_gating()
1365 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1370 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_3_stop_dpg_mode()
1372 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1413 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, in vcn_v4_0_3_stop()
1422 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1433 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1709 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, in vcn_v4_0_3_wait_for_idle()
H A Dvpe_v6_1.c292 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ_6_1_1, 0, in vpe_v_6_1_ring_stop()
296 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, in vpe_v_6_1_ring_stop()
H A Dsoc15_common.h100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro
H A Djpeg_v2_5.c547 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()
H A Djpeg_v4_0_3.c549 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, in jpeg_v4_0_3_start_inst()