1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * TI SN65DSI83,84,85 driver
4 *
5 * Currently supported:
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
15 * (should be easy to add by someone who has the HW)
16 * - SN65DSI85
17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS
18 * - Unsupported
19 * (should be easy to add by someone who has the HW)
20 *
21 * Copyright (C) 2021 Marek Vasut <marex@denx.de>
22 *
23 * Based on previous work of:
24 * Valentin Raevsky <valentin@compulab.co.il>
25 * Philippe Schenker <philippe.schenker@toradex.com>
26 */
27
28 #include <linux/bits.h>
29 #include <linux/clk.h>
30 #include <linux/gpio/consumer.h>
31 #include <linux/i2c.h>
32 #include <linux/media-bus-format.h>
33 #include <linux/module.h>
34 #include <linux/of.h>
35 #include <linux/of_graph.h>
36 #include <linux/regmap.h>
37 #include <linux/regulator/consumer.h>
38 #include <linux/timer.h>
39 #include <linux/workqueue.h>
40
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_bridge.h>
43 #include <drm/drm_bridge_helper.h>
44 #include <drm/drm_mipi_dsi.h>
45 #include <drm/drm_of.h>
46 #include <drm/drm_print.h>
47 #include <drm/drm_probe_helper.h>
48
49 /* ID registers */
50 #define REG_ID(n) (0x00 + (n))
51 /* Reset and clock registers */
52 #define REG_RC_RESET 0x09
53 #define REG_RC_RESET_SOFT_RESET BIT(0)
54 #define REG_RC_LVDS_PLL 0x0a
55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7)
56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1)
57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0)
58 #define REG_RC_DSI_CLK 0x0b
59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3)
60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3)
61 #define REG_RC_PLL_EN 0x0d
62 #define REG_RC_PLL_EN_PLL_EN BIT(0)
63 /* DSI registers */
64 #define REG_DSI_LANE 0x10
65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */
66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */
67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */
68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5)
69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3)
70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1)
71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0)
72 #define REG_DSI_EQ 0x11
73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6)
74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2)
75 #define REG_DSI_CLK 0x12
76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff)
77 /* LVDS registers */
78 #define REG_LVDS_FMT 0x18
79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7)
80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6)
81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5)
82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */
83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3)
84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2)
85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1)
86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0)
87 #define REG_LVDS_VCOM 0x19
88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6)
89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4)
90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2)
91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3)
92 #define REG_LVDS_LANE 0x1a
93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6)
94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5)
95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4)
96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1)
97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0)
98 #define REG_LVDS_CM 0x1b
99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4)
100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3)
101 /* Video registers */
102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20
103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21
104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24
105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25
106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28
107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29
108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c
109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d
110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30
111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31
112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34
113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36
114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38
115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a
116 #define REG_VID_CHA_TEST_PATTERN 0x3c
117 /* IRQ registers */
118 #define REG_IRQ_GLOBAL 0xe0
119 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0)
120 #define REG_IRQ_EN 0xe1
121 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7)
122 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6)
123 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5)
124 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4)
125 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3)
126 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2)
127 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0)
128 #define REG_IRQ_STAT 0xe5
129 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7)
130 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6)
131 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5)
132 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4)
133 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3)
134 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2)
135 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0)
136
137 enum sn65dsi83_channel {
138 CHANNEL_A,
139 CHANNEL_B
140 };
141
142 enum sn65dsi83_lvds_term {
143 OHM_100,
144 OHM_200
145 };
146
147 enum sn65dsi83_model {
148 MODEL_SN65DSI83,
149 MODEL_SN65DSI84,
150 };
151
152 struct sn65dsi83 {
153 struct drm_bridge bridge;
154 struct device *dev;
155 struct regmap *regmap;
156 struct mipi_dsi_device *dsi;
157 struct drm_bridge *panel_bridge;
158 struct gpio_desc *enable_gpio;
159 struct regulator *vcc;
160 bool lvds_dual_link;
161 bool lvds_dual_link_even_odd_swap;
162 int lvds_vod_swing_conf[2];
163 int lvds_term_conf[2];
164 int irq;
165 struct delayed_work monitor_work;
166 struct work_struct reset_work;
167 };
168
169 static const struct regmap_range sn65dsi83_readable_ranges[] = {
170 regmap_reg_range(REG_ID(0), REG_ID(8)),
171 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK),
172 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
173 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
174 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
175 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
176 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
177 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
178 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
179 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
180 REG_VID_CHA_SYNC_DELAY_HIGH),
181 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
182 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
183 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
184 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
185 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
186 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
187 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
188 REG_VID_CHA_VERTICAL_BACK_PORCH),
189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
190 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
191 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
192 REG_VID_CHA_VERTICAL_FRONT_PORCH),
193 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
194 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
195 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
196 };
197
198 static const struct regmap_access_table sn65dsi83_readable_table = {
199 .yes_ranges = sn65dsi83_readable_ranges,
200 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges),
201 };
202
203 static const struct regmap_range sn65dsi83_writeable_ranges[] = {
204 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK),
205 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN),
206 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK),
207 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM),
208 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
209 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH),
210 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
211 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH),
212 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW,
213 REG_VID_CHA_SYNC_DELAY_HIGH),
214 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
215 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH),
216 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
217 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH),
218 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH,
219 REG_VID_CHA_HORIZONTAL_BACK_PORCH),
220 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH,
221 REG_VID_CHA_VERTICAL_BACK_PORCH),
222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
223 REG_VID_CHA_HORIZONTAL_FRONT_PORCH),
224 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH,
225 REG_VID_CHA_VERTICAL_FRONT_PORCH),
226 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN),
227 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN),
228 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
229 };
230
231 static const struct regmap_access_table sn65dsi83_writeable_table = {
232 .yes_ranges = sn65dsi83_writeable_ranges,
233 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges),
234 };
235
236 static const struct regmap_range sn65dsi83_volatile_ranges[] = {
237 regmap_reg_range(REG_RC_RESET, REG_RC_RESET),
238 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL),
239 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT),
240 };
241
242 static const struct regmap_access_table sn65dsi83_volatile_table = {
243 .yes_ranges = sn65dsi83_volatile_ranges,
244 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges),
245 };
246
247 static const struct regmap_config sn65dsi83_regmap_config = {
248 .reg_bits = 8,
249 .val_bits = 8,
250 .rd_table = &sn65dsi83_readable_table,
251 .wr_table = &sn65dsi83_writeable_table,
252 .volatile_table = &sn65dsi83_volatile_table,
253 .cache_type = REGCACHE_MAPLE,
254 .max_register = REG_IRQ_STAT,
255 };
256
257 static const int lvds_vod_swing_data_table[2][4][2] = {
258 { /* 100 Ohm */
259 { 180000, 313000 },
260 { 215000, 372000 },
261 { 250000, 430000 },
262 { 290000, 488000 },
263 },
264 { /* 200 Ohm */
265 { 150000, 261000 },
266 { 200000, 346000 },
267 { 250000, 428000 },
268 { 300000, 511000 },
269 },
270 };
271
272 static const int lvds_vod_swing_clock_table[2][4][2] = {
273 { /* 100 Ohm */
274 { 140000, 244000 },
275 { 168000, 290000 },
276 { 195000, 335000 },
277 { 226000, 381000 },
278 },
279 { /* 200 Ohm */
280 { 117000, 204000 },
281 { 156000, 270000 },
282 { 195000, 334000 },
283 { 234000, 399000 },
284 },
285 };
286
bridge_to_sn65dsi83(struct drm_bridge * bridge)287 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge)
288 {
289 return container_of(bridge, struct sn65dsi83, bridge);
290 }
291
sn65dsi83_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)292 static int sn65dsi83_attach(struct drm_bridge *bridge,
293 struct drm_encoder *encoder,
294 enum drm_bridge_attach_flags flags)
295 {
296 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
297
298 return drm_bridge_attach(encoder, ctx->panel_bridge,
299 &ctx->bridge, flags);
300 }
301
sn65dsi83_detach(struct drm_bridge * bridge)302 static void sn65dsi83_detach(struct drm_bridge *bridge)
303 {
304 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
305
306 if (!ctx->dsi)
307 return;
308
309 ctx->dsi = NULL;
310 }
311
sn65dsi83_get_lvds_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)312 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx,
313 const struct drm_display_mode *mode)
314 {
315 /*
316 * The encoding of the LVDS_CLK_RANGE is as follows:
317 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz
318 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz
319 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz
320 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz
321 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz
322 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz
323 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that
324 * the ends of the ranges are clamped to the supported range. Since
325 * sn65dsi83_mode_valid() already filters the valid modes and limits
326 * the clock to 25..154 MHz, the range calculation can be simplified
327 * as follows:
328 */
329 int mode_clock = mode->clock;
330
331 if (ctx->lvds_dual_link)
332 mode_clock /= 2;
333
334 return (mode_clock - 12500) / 25000;
335 }
336
sn65dsi83_get_dsi_range(struct sn65dsi83 * ctx,const struct drm_display_mode * mode)337 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx,
338 const struct drm_display_mode *mode)
339 {
340 /*
341 * The encoding of the CHA_DSI_CLK_RANGE is as follows:
342 * 0x00 through 0x07 - Reserved
343 * 0x08 - 40 <= DSI_CLK < 45 MHz
344 * 0x09 - 45 <= DSI_CLK < 50 MHz
345 * ...
346 * 0x63 - 495 <= DSI_CLK < 500 MHz
347 * 0x64 - 500 MHz
348 * 0x65 through 0xFF - Reserved
349 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz.
350 * The DSI clock are calculated as:
351 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2
352 * the 2 is there because the bus is DDR.
353 */
354 return DIV_ROUND_UP(clamp((unsigned int)mode->clock *
355 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) /
356 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U);
357 }
358
sn65dsi83_get_dsi_div(struct sn65dsi83 * ctx)359 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx)
360 {
361 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */
362 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format);
363
364 dsi_div /= ctx->dsi->lanes;
365
366 if (!ctx->lvds_dual_link)
367 dsi_div /= 2;
368
369 return dsi_div - 1;
370 }
371
sn65dsi83_reset_pipe(struct sn65dsi83 * sn65dsi83)372 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83)
373 {
374 struct drm_modeset_acquire_ctx ctx;
375 int err;
376
377 /*
378 * Reset active outputs of the related CRTC.
379 *
380 * This way, drm core will reconfigure each components in the CRTC
381 * outputs path. In our case, this will force the previous component to
382 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83
383 * bridge.
384 *
385 * Keep the lock during the whole operation to be atomic.
386 */
387
388 drm_modeset_acquire_init(&ctx, 0);
389
390 dev_warn(sn65dsi83->dev, "reset the pipe\n");
391
392 retry:
393 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx);
394 if (err == -EDEADLK) {
395 drm_modeset_backoff(&ctx);
396 goto retry;
397 }
398
399 drm_modeset_drop_locks(&ctx);
400 drm_modeset_acquire_fini(&ctx);
401
402 return 0;
403 }
404
sn65dsi83_reset_work(struct work_struct * ws)405 static void sn65dsi83_reset_work(struct work_struct *ws)
406 {
407 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work);
408 int ret;
409
410 /* Reset the pipe */
411 ret = sn65dsi83_reset_pipe(ctx);
412 if (ret) {
413 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret));
414 return;
415 }
416 if (ctx->irq)
417 enable_irq(ctx->irq);
418 }
419
sn65dsi83_handle_errors(struct sn65dsi83 * ctx)420 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx)
421 {
422 unsigned int irq_stat;
423 int ret;
424
425 /*
426 * Schedule a reset in case of:
427 * - the bridge doesn't answer
428 * - the bridge signals an error
429 */
430
431 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat);
432 if (ret || irq_stat) {
433 /*
434 * IRQ acknowledged is not always possible (the bridge can be in
435 * a state where it doesn't answer anymore). To prevent an
436 * interrupt storm, disable interrupt. The interrupt will be
437 * after the reset.
438 */
439 if (ctx->irq)
440 disable_irq_nosync(ctx->irq);
441
442 schedule_work(&ctx->reset_work);
443 }
444 }
445
sn65dsi83_monitor_work(struct work_struct * work)446 static void sn65dsi83_monitor_work(struct work_struct *work)
447 {
448 struct sn65dsi83 *ctx = container_of(to_delayed_work(work),
449 struct sn65dsi83, monitor_work);
450
451 sn65dsi83_handle_errors(ctx);
452
453 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
454 }
455
sn65dsi83_monitor_start(struct sn65dsi83 * ctx)456 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx)
457 {
458 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000));
459 }
460
sn65dsi83_monitor_stop(struct sn65dsi83 * ctx)461 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx)
462 {
463 cancel_delayed_work_sync(&ctx->monitor_work);
464 }
465
sn65dsi83_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)466 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge,
467 struct drm_atomic_state *state)
468 {
469 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
470 const struct drm_bridge_state *bridge_state;
471 const struct drm_crtc_state *crtc_state;
472 const struct drm_display_mode *mode;
473 struct drm_connector *connector;
474 struct drm_crtc *crtc;
475 bool lvds_format_24bpp;
476 bool lvds_format_jeida;
477 unsigned int pval;
478 __le16 le16val;
479 u16 val;
480 int ret;
481
482 ret = regulator_enable(ctx->vcc);
483 if (ret) {
484 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret);
485 return;
486 }
487
488 /* Deassert reset */
489 gpiod_set_value_cansleep(ctx->enable_gpio, 1);
490 usleep_range(10000, 11000);
491
492 /* Get the LVDS format from the bridge state. */
493 bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
494
495 switch (bridge_state->output_bus_cfg.format) {
496 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
497 lvds_format_24bpp = false;
498 lvds_format_jeida = true;
499 break;
500 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
501 lvds_format_24bpp = true;
502 lvds_format_jeida = true;
503 break;
504 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
505 lvds_format_24bpp = true;
506 lvds_format_jeida = false;
507 break;
508 default:
509 /*
510 * Some bridges still don't set the correct
511 * LVDS bus pixel format, use SPWG24 default
512 * format until those are fixed.
513 */
514 lvds_format_24bpp = true;
515 lvds_format_jeida = false;
516 dev_warn(ctx->dev,
517 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n",
518 bridge_state->output_bus_cfg.format);
519 break;
520 }
521
522 /*
523 * Retrieve the CRTC adjusted mode. This requires a little dance to go
524 * from the bridge to the encoder, to the connector and to the CRTC.
525 */
526 connector = drm_atomic_get_new_connector_for_encoder(state,
527 bridge->encoder);
528 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
529 crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
530 mode = &crtc_state->adjusted_mode;
531
532 /* Clear reset, disable PLL */
533 regmap_write(ctx->regmap, REG_RC_RESET, 0x00);
534 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
535
536 /* Reference clock derived from DSI link clock. */
537 regmap_write(ctx->regmap, REG_RC_LVDS_PLL,
538 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) |
539 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY);
540 regmap_write(ctx->regmap, REG_DSI_CLK,
541 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode)));
542 regmap_write(ctx->regmap, REG_RC_DSI_CLK,
543 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx)));
544
545 /* Set number of DSI lanes and LVDS link config. */
546 regmap_write(ctx->regmap, REG_DSI_LANE,
547 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE |
548 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) |
549 /* CHB is DSI85-only, set to default on DSI83/DSI84 */
550 REG_DSI_LANE_CHB_DSI_LANES(3));
551 /* No equalization. */
552 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00);
553
554 /* Set up sync signal polarity. */
555 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ?
556 REG_LVDS_FMT_HS_NEG_POLARITY : 0) |
557 (mode->flags & DRM_MODE_FLAG_NVSYNC ?
558 REG_LVDS_FMT_VS_NEG_POLARITY : 0);
559 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ?
560 REG_LVDS_FMT_DE_NEG_POLARITY : 0;
561
562 /* Set up bits-per-pixel, 18bpp or 24bpp. */
563 if (lvds_format_24bpp) {
564 val |= REG_LVDS_FMT_CHA_24BPP_MODE;
565 if (ctx->lvds_dual_link)
566 val |= REG_LVDS_FMT_CHB_24BPP_MODE;
567 }
568
569 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */
570 if (lvds_format_jeida) {
571 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1;
572 if (ctx->lvds_dual_link)
573 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1;
574 }
575
576 /* Set up LVDS output config (DSI84,DSI85) */
577 if (!ctx->lvds_dual_link)
578 val |= REG_LVDS_FMT_LVDS_LINK_CFG;
579
580 regmap_write(ctx->regmap, REG_LVDS_FMT, val);
581 regmap_write(ctx->regmap, REG_LVDS_VCOM,
582 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) |
583 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B]));
584 regmap_write(ctx->regmap, REG_LVDS_LANE,
585 (ctx->lvds_dual_link_even_odd_swap ?
586 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
587 (ctx->lvds_term_conf[CHANNEL_A] ?
588 REG_LVDS_LANE_CHA_LVDS_TERM : 0) |
589 (ctx->lvds_term_conf[CHANNEL_B] ?
590 REG_LVDS_LANE_CHB_LVDS_TERM : 0));
591 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
592
593 le16val = cpu_to_le16(mode->hdisplay);
594 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW,
595 &le16val, 2);
596 le16val = cpu_to_le16(mode->vdisplay);
597 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW,
598 &le16val, 2);
599 /* 32 + 1 pixel clock to ensure proper operation */
600 le16val = cpu_to_le16(32 + 1);
601 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2);
602 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start);
603 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW,
604 &le16val, 2);
605 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start);
606 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW,
607 &le16val, 2);
608 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH,
609 mode->htotal - mode->hsync_end);
610 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH,
611 mode->vtotal - mode->vsync_end);
612 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH,
613 mode->hsync_start - mode->hdisplay);
614 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH,
615 mode->vsync_start - mode->vdisplay);
616 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00);
617
618 /* Enable PLL */
619 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN);
620 usleep_range(3000, 4000);
621 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval,
622 pval & REG_RC_LVDS_PLL_PLL_EN_STAT,
623 1000, 100000);
624 if (ret) {
625 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret);
626 /* On failure, disable PLL again and exit. */
627 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00);
628 return;
629 }
630
631 /* Trigger reset after CSR register update. */
632 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET);
633
634 /* Wait for 10ms after soft reset as specified in datasheet */
635 usleep_range(10000, 12000);
636 }
637
sn65dsi83_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)638 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
639 struct drm_atomic_state *state)
640 {
641 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
642 unsigned int pval;
643
644 /* Clear all errors that got asserted during initialization. */
645 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
646 regmap_write(ctx->regmap, REG_IRQ_STAT, pval);
647
648 /* Wait for 1ms and check for errors in status register */
649 usleep_range(1000, 1100);
650 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval);
651 if (pval)
652 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval);
653
654 if (ctx->irq) {
655 /* Enable irq to detect errors */
656 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN);
657 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff);
658 } else {
659 /* Use the polling task */
660 sn65dsi83_monitor_start(ctx);
661 }
662 }
663
sn65dsi83_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)664 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge,
665 struct drm_atomic_state *state)
666 {
667 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge);
668 int ret;
669
670 if (ctx->irq) {
671 /* Disable irq */
672 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0);
673 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0);
674 } else {
675 /* Stop the polling task */
676 sn65dsi83_monitor_stop(ctx);
677 }
678
679 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
680 gpiod_set_value_cansleep(ctx->enable_gpio, 0);
681 usleep_range(10000, 11000);
682
683 ret = regulator_disable(ctx->vcc);
684 if (ret)
685 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret);
686
687 regcache_mark_dirty(ctx->regmap);
688 }
689
690 static enum drm_mode_status
sn65dsi83_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)691 sn65dsi83_mode_valid(struct drm_bridge *bridge,
692 const struct drm_display_info *info,
693 const struct drm_display_mode *mode)
694 {
695 /* LVDS output clock range 25..154 MHz */
696 if (mode->clock < 25000)
697 return MODE_CLOCK_LOW;
698 if (mode->clock > 154000)
699 return MODE_CLOCK_HIGH;
700
701 return MODE_OK;
702 }
703
704 #define MAX_INPUT_SEL_FORMATS 1
705
706 static u32 *
sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)707 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
708 struct drm_bridge_state *bridge_state,
709 struct drm_crtc_state *crtc_state,
710 struct drm_connector_state *conn_state,
711 u32 output_fmt,
712 unsigned int *num_input_fmts)
713 {
714 u32 *input_fmts;
715
716 *num_input_fmts = 0;
717
718 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
719 GFP_KERNEL);
720 if (!input_fmts)
721 return NULL;
722
723 /* This is the DSI-end bus format */
724 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
725 *num_input_fmts = 1;
726
727 return input_fmts;
728 }
729
730 static const struct drm_bridge_funcs sn65dsi83_funcs = {
731 .attach = sn65dsi83_attach,
732 .detach = sn65dsi83_detach,
733 .atomic_enable = sn65dsi83_atomic_enable,
734 .atomic_pre_enable = sn65dsi83_atomic_pre_enable,
735 .atomic_disable = sn65dsi83_atomic_disable,
736 .mode_valid = sn65dsi83_mode_valid,
737
738 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
739 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
740 .atomic_reset = drm_atomic_helper_bridge_reset,
741 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts,
742 };
743
sn65dsi83_select_lvds_vod_swing(struct device * dev,u32 lvds_vod_swing_data[2],u32 lvds_vod_swing_clk[2],u8 lvds_term)744 static int sn65dsi83_select_lvds_vod_swing(struct device *dev,
745 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term)
746 {
747 int i;
748
749 for (i = 0; i <= 3; i++) {
750 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] &&
751 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] &&
752 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] &&
753 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1])
754 return i;
755 }
756
757 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n");
758 return -EINVAL;
759 }
760
sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 * ctx,int channel)761 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
762 {
763 struct device *dev = ctx->dev;
764 struct device_node *endpoint;
765 int endpoint_reg;
766 /* Set so the property can be freely selected if not defined */
767 u32 lvds_vod_swing_data[2] = { 0, 1000000 };
768 u32 lvds_vod_swing_clk[2] = { 0, 1000000 };
769 /* Set default near end terminataion to 200 Ohm */
770 u32 lvds_term = 200;
771 int lvds_vod_swing_conf;
772 int ret = 0;
773 int ret_data;
774 int ret_clock;
775
776 if (channel == CHANNEL_A)
777 endpoint_reg = 2;
778 else
779 endpoint_reg = 3;
780
781 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1);
782
783 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term);
784 if (lvds_term == 100)
785 ctx->lvds_term_conf[channel] = OHM_100;
786 else if (lvds_term == 200)
787 ctx->lvds_term_conf[channel] = OHM_200;
788 else {
789 ret = -EINVAL;
790 goto exit;
791 }
792
793 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt",
794 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data));
795 if (ret_data != 0 && ret_data != -EINVAL) {
796 ret = ret_data;
797 goto exit;
798 }
799
800 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt",
801 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk));
802 if (ret_clock != 0 && ret_clock != -EINVAL) {
803 ret = ret_clock;
804 goto exit;
805 }
806
807 /* Use default value if both properties are NOT defined. */
808 if (ret_data == -EINVAL && ret_clock == -EINVAL)
809 lvds_vod_swing_conf = 0x1;
810
811 /* Use lookup table if any of the two properties is defined. */
812 if (!ret_data || !ret_clock) {
813 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data,
814 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]);
815 if (lvds_vod_swing_conf < 0) {
816 ret = lvds_vod_swing_conf;
817 goto exit;
818 }
819 }
820
821 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf;
822 ret = 0;
823 exit:
824 of_node_put(endpoint);
825 return ret;
826 }
827
sn65dsi83_parse_dt(struct sn65dsi83 * ctx,enum sn65dsi83_model model)828 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model)
829 {
830 struct drm_bridge *panel_bridge;
831 struct device *dev = ctx->dev;
832 int ret;
833
834 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A);
835 if (ret < 0)
836 return ret;
837
838 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B);
839 if (ret < 0)
840 return ret;
841
842 ctx->lvds_dual_link = false;
843 ctx->lvds_dual_link_even_odd_swap = false;
844 if (model != MODEL_SN65DSI83) {
845 struct device_node *port2, *port3;
846 int dual_link;
847
848 port2 = of_graph_get_port_by_id(dev->of_node, 2);
849 port3 = of_graph_get_port_by_id(dev->of_node, 3);
850 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3);
851 of_node_put(port2);
852 of_node_put(port3);
853
854 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) {
855 ctx->lvds_dual_link = true;
856 /* Odd pixels to LVDS Channel A, even pixels to B */
857 ctx->lvds_dual_link_even_odd_swap = false;
858 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) {
859 ctx->lvds_dual_link = true;
860 /* Even pixels to LVDS Channel A, odd pixels to B */
861 ctx->lvds_dual_link_even_odd_swap = true;
862 }
863 }
864
865 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0);
866 if (IS_ERR(panel_bridge))
867 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n");
868
869 ctx->panel_bridge = panel_bridge;
870
871 ctx->vcc = devm_regulator_get(dev, "vcc");
872 if (IS_ERR(ctx->vcc))
873 return dev_err_probe(dev, PTR_ERR(ctx->vcc),
874 "Failed to get supply 'vcc'\n");
875
876 return 0;
877 }
878
sn65dsi83_host_attach(struct sn65dsi83 * ctx)879 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx)
880 {
881 struct device *dev = ctx->dev;
882 struct device_node *host_node;
883 struct device_node *endpoint;
884 struct mipi_dsi_device *dsi;
885 struct mipi_dsi_host *host;
886 const struct mipi_dsi_device_info info = {
887 .type = "sn65dsi83",
888 .channel = 0,
889 .node = NULL,
890 };
891 int dsi_lanes, ret;
892
893 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
894 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4);
895 host_node = of_graph_get_remote_port_parent(endpoint);
896 host = of_find_mipi_dsi_host_by_node(host_node);
897 of_node_put(host_node);
898 of_node_put(endpoint);
899
900 if (!host)
901 return -EPROBE_DEFER;
902
903 if (dsi_lanes < 0)
904 return dsi_lanes;
905
906 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
907 if (IS_ERR(dsi))
908 return dev_err_probe(dev, PTR_ERR(dsi),
909 "failed to create dsi device\n");
910
911 ctx->dsi = dsi;
912
913 dsi->lanes = dsi_lanes;
914 dsi->format = MIPI_DSI_FMT_RGB888;
915 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
916 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP |
917 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET;
918
919 ret = devm_mipi_dsi_attach(dev, dsi);
920 if (ret < 0) {
921 dev_err(dev, "failed to attach dsi to host: %d\n", ret);
922 return ret;
923 }
924
925 return 0;
926 }
927
sn65dsi83_irq(int irq,void * data)928 static irqreturn_t sn65dsi83_irq(int irq, void *data)
929 {
930 struct sn65dsi83 *ctx = data;
931
932 sn65dsi83_handle_errors(ctx);
933 return IRQ_HANDLED;
934 }
935
sn65dsi83_probe(struct i2c_client * client)936 static int sn65dsi83_probe(struct i2c_client *client)
937 {
938 const struct i2c_device_id *id = i2c_client_get_device_id(client);
939 struct device *dev = &client->dev;
940 enum sn65dsi83_model model;
941 struct sn65dsi83 *ctx;
942 int ret;
943
944 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs);
945 if (IS_ERR(ctx))
946 return PTR_ERR(ctx);
947
948 ctx->dev = dev;
949 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work);
950 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work);
951
952 if (dev->of_node) {
953 model = (enum sn65dsi83_model)(uintptr_t)
954 of_device_get_match_data(dev);
955 } else {
956 model = id->driver_data;
957 }
958
959 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */
960 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable",
961 GPIOD_OUT_LOW);
962 if (IS_ERR(ctx->enable_gpio))
963 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n");
964
965 usleep_range(10000, 11000);
966
967 ret = sn65dsi83_parse_dt(ctx, model);
968 if (ret)
969 return ret;
970
971 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config);
972 if (IS_ERR(ctx->regmap))
973 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n");
974
975 if (client->irq) {
976 ctx->irq = client->irq;
977 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq,
978 IRQF_ONESHOT, dev_name(ctx->dev), ctx);
979 if (ret)
980 return dev_err_probe(dev, ret, "failed to request irq\n");
981 }
982
983 dev_set_drvdata(dev, ctx);
984 i2c_set_clientdata(client, ctx);
985
986 ctx->bridge.of_node = dev->of_node;
987 ctx->bridge.pre_enable_prev_first = true;
988 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS;
989 drm_bridge_add(&ctx->bridge);
990
991 ret = sn65dsi83_host_attach(ctx);
992 if (ret) {
993 dev_err_probe(dev, ret, "failed to attach DSI host\n");
994 goto err_remove_bridge;
995 }
996
997 return 0;
998
999 err_remove_bridge:
1000 drm_bridge_remove(&ctx->bridge);
1001 return ret;
1002 }
1003
sn65dsi83_remove(struct i2c_client * client)1004 static void sn65dsi83_remove(struct i2c_client *client)
1005 {
1006 struct sn65dsi83 *ctx = i2c_get_clientdata(client);
1007
1008 drm_bridge_remove(&ctx->bridge);
1009 }
1010
1011 static const struct i2c_device_id sn65dsi83_id[] = {
1012 { "ti,sn65dsi83", MODEL_SN65DSI83 },
1013 { "ti,sn65dsi84", MODEL_SN65DSI84 },
1014 {},
1015 };
1016 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id);
1017
1018 static const struct of_device_id sn65dsi83_match_table[] = {
1019 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 },
1020 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 },
1021 {},
1022 };
1023 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table);
1024
1025 static struct i2c_driver sn65dsi83_driver = {
1026 .probe = sn65dsi83_probe,
1027 .remove = sn65dsi83_remove,
1028 .id_table = sn65dsi83_id,
1029 .driver = {
1030 .name = "sn65dsi83",
1031 .of_match_table = sn65dsi83_match_table,
1032 },
1033 };
1034 module_i2c_driver(sn65dsi83_driver);
1035
1036 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1037 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver");
1038 MODULE_LICENSE("GPL v2");
1039