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Searched refs:MAX_PIPES (Results 1 – 25 of 66) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/inc/ !
H A Dcore_types.h244 struct mem_input *mis[MAX_PIPES];
245 struct hubp *hubps[MAX_PIPES];
246 struct input_pixel_processor *ipps[MAX_PIPES];
247 struct transform *transforms[MAX_PIPES];
248 struct dpp *dpps[MAX_PIPES];
249 struct output_pixel_processor *opps[MAX_PIPES];
250 struct timing_generator *timing_generators[MAX_PIPES];
251 struct stream_encoder *stream_enc[MAX_PIPES * 2];
255 struct dce_aux *engines[MAX_PIPES];
256 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
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H A Dresource.h389 struct pipe_ctx *opp_heads[MAX_PIPES]);
399 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
408 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
/linux/drivers/gpu/drm/amd/display/dc/core/ !
H A Ddc_link_enc_cfg.c101 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment()
237 for (i = 0; i < MAX_PIPES; i++) { in get_link_enc_used_by_link()
253 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments()
303 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign()
399 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
405 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
418 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
469 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc()
508 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link()
532 for (i = 0; i < MAX_PIPES; in link_enc_cfg_get_next_avail_link_enc()
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H A Ddc_stream.c240 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
369 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
645 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
675 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
708 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
735 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
741 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
765 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
771 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
807 for (i = 0; i < MAX_PIPES; in dc_stream_get_pipe_ctx()
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H A Ddc.c410 for (i = 0; i < MAX_PIPES; i++) { in set_long_vtotal()
472 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
509 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
575 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_crc_window()
582 if (i == MAX_PIPES) in dc_stream_forward_crc_window()
641 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_multiple_crc_window()
648 if (i == MAX_PIPES) in dc_stream_forward_multiple_crc_window()
764 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
770 if (i == MAX_PIPES) in dc_stream_get_crc()
790 for (i = 0; i < MAX_PIPES; in dc_stream_set_dyn_expansion()
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H A Ddc_resource.c690 for (i = 0; i < MAX_PIPES; i++) { in resource_find_used_clk_src_for_sharing()
1407 struct pipe_ctx *opp_heads[MAX_PIPES]; in resource_build_test_pattern_params()
1699 for (i = 0; i < MAX_PIPES; i++) { in resource_build_scaling_params_for_context()
1953 for (i = 0; i < MAX_PIPES; i++) { in resource_get_otg_master_for_stream()
1963 struct pipe_ctx *opp_heads[MAX_PIPES]) in resource_get_opp_heads_for_otg_master() argument
1979 ASSERT(i < MAX_PIPES); in resource_get_opp_heads_for_otg_master()
1988 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_opp_head() argument
1998 ASSERT(i < MAX_PIPES); in resource_get_dpp_pipes_for_opp_head()
2007 struct pipe_ctx *dpp_pipes[MAX_PIPES]) in resource_get_dpp_pipes_for_plane() argument
2012 for (j = 0; j < MAX_PIPES; in resource_get_dpp_pipes_for_plane()
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/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/ !
H A Ddcn20_dccg.h132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
171 type DTBCLK_DTO_DIV[MAX_PIPES];\
360 type DP_DTO_ENABLE[MAX_PIPES];
387 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
394 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
395 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
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/linux/drivers/gpu/drm/amd/display/dc/dml2/ !
H A Ddml2_internal_types.h131 struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];
132 struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];
H A Ddml2_dc_resource_mgmt.c47 unsigned int odm_slice_end_x[MAX_PIPES];
48 struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
187 // unsigned int pipes_assigned_to_plane[MAX_PIPES]; in validate_pipe_assignment()
349 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
350 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_pipes_for_stream()
415 unsigned int preferred_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
416 unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0}; in find_more_free_pipes()
614 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_stream()
652 unsigned int pipes[MAX_PIPES] = {0}; in assign_pipes_to_plane()
913 struct pipe_ctx *dpp_pipes[MAX_PIPES] in get_source_mpc_factor()
929 populate_mpc_factors_for_stream(struct dml2_context * ctx,const struct dml_display_cfg_st * disp_cfg,struct dml2_dml_to_dc_pipe_mapping * mapping,struct dc_state * state,unsigned int stream_idx,struct dml2_pipe_combine_factor odm_factor,struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) populate_mpc_factors_for_stream() argument
945 populate_odm_factors(const struct dml2_context * ctx,const struct dml_display_cfg_st * disp_cfg,struct dml2_dml_to_dc_pipe_mapping * mapping,struct dc_state * state,struct dml2_pipe_combine_factor odm_factors[MAX_PIPES]) populate_odm_factors() argument
962 unmap_dc_pipes_for_stream(struct dml2_context * ctx,struct dc_state * state,const struct dc_state * existing_state,const struct dc_stream_state * stream,const struct dc_stream_status * status,struct dml2_pipe_combine_factor odm_factor,struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) unmap_dc_pipes_for_stream() argument
991 map_dc_pipes_for_stream(struct dml2_context * ctx,struct dc_state * state,const struct dc_state * existing_state,const struct dc_stream_state * stream,const struct dc_stream_status * status,struct dml2_pipe_combine_factor odm_factor,struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES]) map_dc_pipes_for_stream() argument
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H A Ddml2_wrapper.h100 struct pipe_ctx *opp_heads[MAX_PIPES]);
103 struct pipe_ctx *dpp_pipes[MAX_PIPES]);
236 enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ !
H A Dhw_shared.h40 * @MAX_PIPES:
42 * Every ASIC support a fixed number of pipes; MAX_PIPES defines a large number
45 #define MAX_PIPES 6 macro
46 #define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
47 #define MAX_LINKS (MAX_PIPES * 2 +2)
H A Ddccg.h77 int pipe_dppclk_khz[MAX_PIPES];
79 bool dpp_clock_gated[MAX_PIPES];
80 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
H A Dpg_cntl.h35 bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
/linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ !
H A Ddcn35_pg_cntl.c145 if (dsc_inst < MAX_PIPES) in pg_cntl35_dsc_pg_control()
241 if (hubp_dpp_inst < MAX_PIPES) { in pg_cntl35_hubp_dpp_pg_control()
362 if (mpcc_inst < MAX_PIPES) in pg_cntl35_mpcc_pg_control()
372 if (opp_inst < MAX_PIPES) in pg_cntl35_opp_pg_control()
382 if (optc_inst < MAX_PIPES) in pg_cntl35_optc_pg_control()
539 memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool)); in pg_cntl35_create()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/ !
H A Ddcn401_optc.c59 bool first_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
60 bool second_preferred_memory_for_opp[MAX_PIPES] = {0}; in decide_odm_mem_bit_map()
83 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
94 for (i = 0; i < MAX_PIPES; i++) { in decide_odm_mem_bit_map()
/linux/drivers/gpu/drm/amd/display/dc/dce/ !
H A Ddce_clock_source.h228 uint32_t PHASE[MAX_PIPES];
229 uint32_t MODULO[MAX_PIPES];
230 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
H A Ddmub_replay.c14 #define MAX_PIPES 6 macro
67 for (i = 0; i < MAX_PIPES; i++) { in dmub_replay_enable()
152 for (i = 0; i < MAX_PIPES; i++) { in dmub_replay_copy_settings()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ !
H A Ddcn32_clk_mgr.c514 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn32_auto_dpm_test_log()
517 for (int i = 0; i < MAX_PIPES; i++) { in dcn32_auto_dpm_test_log()
564 uint32_t pix_clk_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
565 int p_state_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
566 int disp_src_width_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
567 int disp_src_height_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
568 uint64_t disp_src_refresh_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
569 bool is_scaled_list[MAX_PIPES] = {0}; in dcn32_auto_dpm_test_log()
/linux/drivers/gpu/drm/amd/display/dc/link/ !
H A Dlink_dpms.h42 struct pipe_ctx *pipes[MAX_PIPES]);
H A Dlink_resource.c40 for (i = 0; i < MAX_PIPES; i++) { in link_get_cur_link_res()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ !
H A Ddcn314_hwseq.c176 int opp_inst[MAX_PIPES] = {0}; in dcn314_update_odm()
402 bool otg_disabled[MAX_PIPES] = {false}; in dcn314_resync_fifo_dccg_dio()
434 int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst }; in dcn314_resync_fifo_dccg_dio()
487 for (i = 0; i < MAX_PIPES; i++) { in apply_symclk_on_tx_off_wa()
/linux/drivers/gpu/drm/amd/display/dc/link/accessories/ !
H A Dlink_dp_cts.c69 struct pipe_ctx *pipes[MAX_PIPES]; in dp_retrain_link_dp_test()
78 struct audio_output audio_output[MAX_PIPES]; in dp_retrain_link_dp_test()
655 for (i = 0; i < MAX_PIPES; i++) { in dp_set_test_pattern()
962 for (i = 0; i < MAX_PIPES; i++) { in dp_set_preferred_link_settings()
973 if (i == MAX_PIPES) in dp_set_preferred_link_settings()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ !
H A Damdgpu_dm_mst_types.c958 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
959 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
1061 bool tried[MAX_PIPES]; in try_disable_dsc()
1062 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
1154 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1317 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1333 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1448 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1518 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
H A Damdgpu_dm_debugfs.c1294 for (i = 0; i < MAX_PIPES; i++) { in odm_combine_segments_show()
1569 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1671 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1755 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1855 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1939 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
2039 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
2119 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
2216 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2294 for (i = 0; i < MAX_PIPES; in dp_dsc_pic_width_read()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ !
H A Ddcn401_clk_mgr.c418 struct pipe_ctx *pipe_ctx_list[MAX_PIPES]; in dcn401_auto_dpm_test_log()
421 for (int i = 0; i < MAX_PIPES; i++) { in dcn401_auto_dpm_test_log()
466 uint32_t pix_clk_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
467 int p_state_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
468 int disp_src_width_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
469 int disp_src_height_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
470 uint64_t disp_src_refresh_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()
471 bool is_scaled_list[MAX_PIPES] = {0}; in dcn401_auto_dpm_test_log()

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