Searched refs:CLK_TOP_IRTX_SEL (Results 1 – 5 of 5) sorted by relevance
| /linux/include/dt-bindings/clock/ |
| H A D | mediatek,mt6735-topckgen.h | 76 #define CLK_TOP_IRTX_SEL 68 macro
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| H A D | mt7629-clk.h | 110 #define CLK_TOP_IRTX_SEL 100 macro
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| H A D | mt7622-clk.h | 95 #define CLK_TOP_IRTX_SEL 83 macro
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| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 362 MUX_GATE_CLR_SET_UPD(CLK_TOP_IRTX_SEL, "irtx_sel", irtx_sel_parents, CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 24, 1, 31, 0, 0),
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| H A D | clk-mt7629.c | 522 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", irrx_parents,
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