Searched refs:BIT11 (Results 1 – 12 of 12) sorted by relevance
42 #define BIT11 0x00000800 macro
160 #define ODM_BIT_BB_ATC_11N BIT11
65 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); in PHY_RF6052SetBandwidth8723B()
376 ODM_BB_PSD = BIT11,
212 PHY_SetBBReg(pDM_Odm->Adapter, REG_RD_CTRL, BIT11, 1); /* stop counting if EDCCA is asserted */ in odm_AdaptivityInit()
232 #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
28 #define BIT11 0x00000800 macro
287 #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */
30 #define BIT11 0x0800 macro
65 #define BIT11 0x00000800 macro
384 #define IRQ_TXUNDER BIT11 /* HDLC */4185 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode() 4186 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode() 4189 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode() 4190 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode() 4258 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode() 4259 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode() 4262 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode() 4263 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
778 #define LPFC_SLI4_INTR11 BIT11