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/linux/drivers/comedi/drivers/ni_routing/ni_route_values/
H A Dni_mseries.c56 [B(NI_PFI(0))] = {
57 [B(TRIGGER_LINE(0))] = I(18),
58 [B(TRIGGER_LINE(1))] = I(19),
59 [B(TRIGGER_LINE(2))] = I(20),
60 [B(TRIGGER_LINE(3))] = I(21),
61 [B(TRIGGER_LINE(4))] = I(22),
62 [B(TRIGGER_LINE(5))] = I(23),
63 [B(TRIGGER_LINE(6))] = I(24),
64 [B(TRIGGER_LINE(7))] = I(25),
65 [B(NI_CtrSourc
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H A Dni_eseries.c53 [B(NI_PFI(0))] = {
54 [B(NI_AI_StartTrigger)] = I(NI_PFI_OUTPUT_AI_START1),
56 [B(NI_PFI(1))] = {
57 [B(NI_AI_ReferenceTrigger)] = I(NI_PFI_OUTPUT_AI_START2),
59 [B(NI_PFI(2))] = {
60 [B(NI_AI_ConvertClock)] = I(NI_PFI_OUTPUT_AI_CONVERT),
62 [B(NI_PFI(3))] = {
63 [B(NI_CtrSource(1))] = I(NI_PFI_OUTPUT_G_SRC1),
65 [B(NI_PFI(4))] = {
66 [B(NI_CtrGat
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H A Dni_660x.c48 [B(NI_PFI(8))] = {
49 [B(NI_CtrInternalOutput(7))] = I(1),
51 [B(NI_PFI(10))] = {
52 [B(NI_CtrGate(7))] = I(1),
54 [B(NI_PFI(11))] = {
55 [B(NI_CtrSource(7))] = I(1),
57 [B(NI_PFI(12))] = {
58 [B(NI_CtrInternalOutput(6))] = I(1),
60 [B(NI_PFI(14))] = {
61 [B(NI_CtrGat
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/linux/rust/kernel/sync/
H A Dlock.rs103 /// [`Backend`] specified as the generic parameter `B`.
106 pub struct Lock<T: ?Sized, B: Backend> {
109 state: Opaque<B::State>,
122 unsafe impl<T: ?Sized + Send, B: Backend> Send for Lock<T, B> {}
126 unsafe impl<T: ?Sized + Send, B: Backend> Sync for Lock<T, B> {}
128 impl<T, B: Backend> Lock<T, B> {
137 B in new()
167 lock(&self) -> Guard<'_, T, B> lock() argument
180 try_lock(&self) -> Option<Guard<'_, T, B>> try_lock() argument
229 lock_ref(&self) -> &'a Lock<T, B> lock_ref() argument
274 new(lock: &'a Lock<T, B>, state: B::GuardState) -> Self new() argument
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/linux/rust/kernel/sync/lock/
H A Dglobal.rs36 pub struct GlobalLock<B: GlobalLockBackend> {
37 inner: Lock<B::Item, B::Backend>,
40 impl<B: GlobalLockBackend> GlobalLock<B> {
46 /// * The type `B` must not be used with any other lock.
47 pub const unsafe fn new(data: B::Item) -> Self { in new()
71 B::Backend::init( in init()
73 B::NAME.as_char_ptr(), in init()
74 B in init()
80 lock(&'static self) -> GlobalGuard<B> lock() argument
87 try_lock(&'static self) -> Option<GlobalGuard<B>> try_lock() argument
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/linux/lib/zstd/common/
H A Dcpu.h162 #define B(name, bit) X(name, f7b, bit) macro
163 B(bmi1, 3)
164 B(hle, 4)
165 B(avx2, 5)
166 B(smep, 7)
167 B(bmi2, 8)
168 B(erms, 9)
169 B(invpcid, 10)
170 B(rtm, 11)
171 B(mp
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/linux/drivers/comedi/drivers/
H A Dni_routes.c32 * #define B(x) ((x) - NI_NAMES_BASE)
163 if (RVi(rv, B(src), B(dest))) in ni_count_valid_routes()
167 (RVi(rv, B(src), B(NI_RGOUT0)) || in ni_count_valid_routes()
168 RVi(rv, B(src), B(NI_RTSI_BRD(0))) || in ni_count_valid_routes()
169 RVi(rv, B(src), B(NI_RTSI_BRD(1))) || in ni_count_valid_routes()
170 RVi(rv, B(sr in ni_count_valid_routes()
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/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-srggb10-ipu3.rst39 - B\ :sub:`0000low`
42 B\ :sub:`0000high`\ (bits 1--0)
43 - B\ :sub:`0002low`\ (bits 7--4)
48 B\ :sub:`0002high`\ (bits 5--0)
51 - B\ :sub:`0004low`
54 B\ :sub:`0004high`\ (bits 1--0)
55 - B\ :sub:`0006low`\ (bits 7--4)
61 B\ :sub:`0006high`\ (bits 5--0)
63 - B\ :sub:`0008low`
66 B\
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H A Dmetafmt-vsp1-hgo.rst31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
36 - In *256 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
67 - B/Cb/V max [7:0]
69 - B/Cb/V min [7:0]
75 - :cspan:`4` B/Cb/V sum [31:0]
89 - :cspan:`4` B/Cb/V bin 0 [31:0]
93 - :cspan:`4` B/Cb/V bin 63 [31:0]
108 - max(R,G,B) max [7:0]
110 - max(R,G,B) min [7:0]
112 - :cspan:`4` max(R,G,B) su
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/linux/scripts/coccinelle/misc/
H A Dboolconv.cocci19 expression A, B;
24 A == B
26 A != B
28 A > B
30 A < B
32 A >= B
34 A <= B
36 A && B
38 A || B
47 expression A, B;
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H A Dexcluded_middle.cocci3 /// Condition !A || A && B is equivalent to !A || B.
15 expression A, B;
19 * !A || (A &&@p B)
22 expression A, B;
26 - (A && B)
27 + B
33 coccilib.report.print_report(p[0], "WARNING !A || A && B is equivalent to !A || B")
39 coccilib.org.print_todo(p[0], "WARNING !A || A && B i
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/linux/Documentation/translations/ko_KR/
H A Dmemory-barriers.txt181 { A == 1; B == 2 }
182 A = 3; x = B;
183 B = 4; y = A;
188 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
189 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
190 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
191 STORE A=3, y=LOAD A->3, x=LOAD B
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/linux/drivers/gpu/drm/i915/selftests/
H A Di915_sw_fence.c98 struct i915_sw_fence *A, *B, *C; in test_dag() local
114 B = alloc_fence(); in test_dag()
115 if (!B) { in test_dag()
120 i915_sw_fence_await_sw_fence_gfp(A, B, GFP_KERNEL); in test_dag()
121 if (i915_sw_fence_await_sw_fence_gfp(B, A, GFP_KERNEL) != -EINVAL) { in test_dag()
132 if (i915_sw_fence_await_sw_fence_gfp(B, C, GFP_KERNEL) == -EINVAL) { in test_dag()
136 if (i915_sw_fence_await_sw_fence_gfp(C, B, GFP_KERNEL) != -EINVAL) { in test_dag()
150 i915_sw_fence_commit(B); in test_dag()
158 if (!i915_sw_fence_done(B)) { in test_dag()
159 pr_err("fence B no in test_dag()
177 struct i915_sw_fence *A, *B; test_AB() local
225 struct i915_sw_fence *A, *B, *C; test_ABC() local
305 struct i915_sw_fence *A, *B, *C; test_AB_C() local
382 struct i915_sw_fence *A, *B, *C; test_C_AB() local
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/linux/arch/arm/mach-omap1/
H A Dmux.c75 MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
76 MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
77 MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
126 MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
130 MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
131 MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
133 MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
134 MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
135 MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
136 MUX_CFG("V9_1610_MMC2_CMDDIR", B, 1
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/linux/lib/crypto/
H A Dsha1.c60 #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ argument
63 B = ror32(B, 2); \
64 TEMP = E; E = D; D = C; C = B; B = A; A = TEMP; } while (0)
66 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
67 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B) argument
68 T_20_39(t,A,B,C,D,E) global() argument
69 T_40_59(t,A,B,C,D,E) global() argument
70 T_60_79(t,A,B,C,D,E) global() argument
92 __u32 A, B, C, D, E; sha1_transform() local
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/linux/lib/crypto/x86/
H A Dsha1-ssse3-and-avx.S114 mov 4(HASH_PTR), B
127 RR F1,A,B,C,D,E,0
128 RR F1,D,E,A,B,C,2
129 RR F1,B,C,D,E,A,4
130 RR F1,E,A,B,C,D,6
131 RR F1,C,D,E,A,B,8
133 RR F1,A,B,C,D,E,10
134 RR F1,D,E,A,B,C,12
135 RR F1,B,C,D,E,A,14
136 RR F1,E,A,B,
192 .set B, REG_B global() define
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/linux/Documentation/translations/zh_CN/driver-api/
H A Dio_ordering.rst34 CPU B: spin_lock_irqsave(&dev_lock, flags)
35 CPU B: val = readl(my_status);
36 CPU B: ...
37 CPU B: writel(newval2, ring_ptr);
38 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
52 CPU B: spin_lock_irqsave(&dev_lock, flags)
53 CPU B: val = readl(my_status);
54 CPU B: ...
55 CPU B: writel(newval2, ring_ptr);
56 CPU B
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/linux/arch/arm/boot/dts/st/
H A Dstm32h7-pinctrl.dtsi49 pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
50 <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
120 <STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
126 pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
135 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
136 <STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
142 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
143 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
144 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
145 <STM32_PINMUX('B',
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H A Dstm32f7-pinctrl.dtsi159 pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
166 pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
167 <STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
191 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
192 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
193 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
194 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
195 <STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
196 <STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
197 <STM32_PINMUX('B',
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H A Dstm32f4-pinctrl.dtsi180 pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
186 pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
204 pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
205 <STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
206 <STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
220 <STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
221 <STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
222 <STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
223 <STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
224 <STM32_PINMUX('B', 1
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/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5_macb1.dtsi19 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC16 periph B */
20 AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC18 periph B */
21 AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC19 periph B */
22 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
23 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
24 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
25 AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC28 periph B */
26 AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC29 periph B */
27 AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC30 periph B */
28 AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
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/linux/tools/testing/selftests/net/netfilter/
H A Dnft_concat_range.sh488 # Setup veth pair: this namespace receives traffic, B generates it
490 ip netns add B
494 ip link set veth_b netns B
496 ip -n B link set veth_b up
505 ip -n B route add default dev veth_b
507 ip -6 -n B addr add fe80::2/64 dev veth_b nodad
508 ip -6 -n B addr add 2001:db8::2/64 dev veth_b nodad
509 ip -6 -n B route add default dev veth_b
511 B() { function
512 ip netns exec B "
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/linux/drivers/comedi/drivers/tests/
H A Dni_routes_test.c28 #define B(x) ((x) - NI_NAMES_BASE) macro
135 [B(NI_RGOUT0)] = {[B(rgout0_src0)] = V(0),
136 [B(rgout0_src1)] = V(1)},
137 [B(NI_RTSI_BRD(0))] = {[B(brd0_src0)] = V(0),
138 [B(brd0_src1)] = V(1)},
139 [B(NI_RTSI_BRD(1))] = {[B(brd1_src0)] = V(0),
140 [B(brd1_src
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/linux/Documentation/usb/
H A Dchipidea.rst39 is micro B plug.
41 The A-device (with micro A plug inserted) should enumerate B-device.
45 On B-device::
49 B-device should take host role and enumerate A-device.
53 On B-device::
57 or, by introducing HNP polling, B-Host can know when A-peripheral wishes to
59 A-peripheral side by answering the polling from B-Host. This can be done on
64 A-device should switch back to host and enumerate B-device.
66 5) Remove B-device (unplug micro B plu
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/linux/drivers/macintosh/
H A Dvia-cuda.c40 #define B 0 /* B-side data */ macro
42 #define DIRB (2*RS) /* B-side direction (1=output) */
74 /* Bits in Port B data register */
111 out_8(&via[B], in_8(&via[B]) | TIP); in assert_TIP()
113 out_8(&via[B], in_8(&via[B]) & ~TIP); in assert_TIP()
120 out_8(&via[B], in_8(&via[B]) | TI in assert_TIP_and_TACK()
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