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Searched refs:vm_manager (Results 1 – 25 of 53) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ids.c203 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
220 struct amdgpu_ring *r = adev->vm_manager.concurrent_flush ? in amdgpu_vmid_grab_idle()
231 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
232 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
278 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_reserved()
294 (!adev->vm_manager.concurrent_flush && needs_flush)) { in amdgpu_vmid_grab_reserved()
300 if (adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_reserved()
343 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
369 if (needs_flush && !adev->vm_manager.concurrent_flush) in amdgpu_vmid_grab_used()
404 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager in amdgpu_vmid_grab()
[all...]
H A Damdgpu_vm.c150 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid)); in amdgpu_vm_set_pasid()
158 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm, in amdgpu_vm_set_pasid()
511 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
512 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
517 adev->vm_manager.vm_pte_scheds, in amdgpu_vm_init_entities()
518 adev->vm_manager.vm_pte_num_scheds, NULL); in amdgpu_vm_init_entities()
731 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
766 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
1315 vram_base = bo_adev->vm_manager.vram_base_offset; in amdgpu_vm_bo_update()
1400 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); in amdgpu_vm_update_prt_state()
[all …]
H A Damdgpu_vm.h55 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \
475 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
476 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
477 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
H A Dgfxhub_v12_0.c175 + adev->vm_manager.vram_base_offset; in gfxhub_v12_0_init_system_aperture_regs()
308 adev->vm_manager.num_level); in gfxhub_v12_0_setup_vmid_config()
325 adev->vm_manager.block_size - 9); in gfxhub_v12_0_setup_vmid_config()
338 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()
341 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()
H A Dmmhub_v4_1_0.c185 adev->vm_manager.vram_base_offset; in mmhub_v4_1_0_init_system_aperture_regs()
322 adev->vm_manager.num_level); in mmhub_v4_1_0_setup_vmid_config()
340 adev->vm_manager.block_size - 9); in mmhub_v4_1_0_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()
356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()
H A Dgmc_v6_0.c446 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()
503 field = adev->vm_manager.fragment_size; in gmc_v6_0_gart_enable()
527 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
548 ((adev->vm_manager.block_size - 9) in gmc_v6_0_gart_enable()
588 adev->vm_manager.saved_table_addr[i] = RREG32(reg); in gmc_v6_0_gart_disable()
873 adev->vm_manager.first_kfd_vmid = 8; in gmc_v6_0_sw_init()
881 adev->vm_manager.vram_base_offset = tmp; in gmc_v6_0_sw_init()
883 adev->vm_manager.vram_base_offset = 0; in gmc_v6_0_sw_init()
H A Dmmhub_v3_0_2.c321 adev->vm_manager.num_level); in mmhub_v3_0_2_setup_vmid_config()
339 adev->vm_manager.block_size - 9); in mmhub_v3_0_2_setup_vmid_config()
352 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
355 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
H A Dgfxhub_v11_5_0.c303 adev->vm_manager.num_level); in gfxhub_v11_5_0_setup_vmid_config()
320 adev->vm_manager.block_size - 9); in gfxhub_v11_5_0_setup_vmid_config()
333 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()
336 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()
H A Dgfxhub_v3_0.c300 adev->vm_manager.num_level); in gfxhub_v3_0_setup_vmid_config()
317 adev->vm_manager.block_size - 9); in gfxhub_v3_0_setup_vmid_config()
330 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
333 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
H A Dmmhub_v2_0.c373 adev->vm_manager.num_level); in mmhub_v2_0_setup_vmid_config()
391 adev->vm_manager.block_size - 9); in mmhub_v2_0_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
H A Dmmhub_v2_3.c291 adev->vm_manager.num_level); in mmhub_v2_3_setup_vmid_config()
309 adev->vm_manager.block_size - 9); in mmhub_v2_3_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
H A Dgmc_v7_0.c576 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
645 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
692 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1052 adev->vm_manager.first_kfd_vmid = 8; in gmc_v7_0_sw_init()
1060 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1062 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
H A Dgmc_v12_0.c474 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v12_0_get_vm_pde()
649 adev->vm_manager.vram_base_offset = 0; in gmc_v12_0_vram_gtt_location()
651 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v12_0_vram_gtt_location()
816 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; in gmc_v12_0_sw_init()
H A Dgmc_v8_0.c791 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
861 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
905 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
930 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1165 adev->vm_manager.first_kfd_vmid = 8; in gmc_v8_0_sw_init()
1173 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1175 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
H A Dmmhub_v1_8.c384 num_level = adev->vm_manager.num_level; in mmhub_v1_8_setup_vmid_config()
385 block_size = adev->vm_manager.block_size; in mmhub_v1_8_setup_vmid_config()
435 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()
439 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()
H A Dmmhub_v1_0.c285 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
286 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
327 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
330 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
H A Dgmc_v9_0.c1684 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
1687 adev->vm_manager.vram_base_offset += in gmc_v9_0_vram_gtt_location()
1911 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1930 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1939 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
1951 adev->gmc.translate_further = adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
2035 adev->vm_manager.first_kfd_vmid = in gmc_v9_0_sw_init()
H A Dgmc_v11_0.c656 adev->vm_manager.vram_base_offset = 0; in gmc_v11_0_vram_gtt_location()
658 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
840 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; in gmc_v11_0_sw_init()
H A Dsi_dma.c845 adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs; in si_dma_set_vm_pte_funcs()
847 adev->vm_manager.vm_pte_scheds[i] = in si_dma_set_vm_pte_funcs()
850 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
H A Dgmc_v10_0.c683 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_vram_gtt_location()
686 adev->vm_manager.vram_base_offset += in gmc_v10_0_vram_gtt_location()
896 adev->vm_manager.first_kfd_vmid = 8; in gmc_v10_0_sw_init()
H A Dmmhub_v1_7.c293 num_level = adev->vm_manager.num_level; in mmhub_v1_7_setup_vmid_config()
294 block_size = adev->vm_manager.block_size; in mmhub_v1_7_setup_vmid_config()
337 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()
340 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()
H A Damdgpu_gmc.c1073 vram_addr = adev->vm_manager.vram_base_offset; in amdgpu_gmc_init_pdb0()
1104 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset; in amdgpu_gmc_vram_mc2pa()
1363 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
1367 adev->vm_manager.vram_base_offset) >> in amdgpu_gmc_get_nps_memranges()
H A Dsdma_v2_4.c1247 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1249 adev->vm_manager.vm_pte_scheds[i] = in sdma_v2_4_set_vm_pte_funcs()
1252 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
187 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
194 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
195 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
214 return rdev->vm_manager in radeon_vm_grab_id()
[all...]
H A Dni.c1300 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1302 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1337 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2481 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2486 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2488 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()

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