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Searched refs:ucode (Results 1 – 25 of 96) sorted by relevance

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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Ducode_loader.c40 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode) in brcms_ucode_data_init() argument
47 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0bsinitvals24, in brcms_ucode_data_init()
50 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn0initvals24, in brcms_ucode_data_init()
53 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1bsinitvals24, in brcms_ucode_data_init()
56 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn1initvals24, in brcms_ucode_data_init()
59 brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2bsinitvals24, in brcms_ucode_data_init()
62 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11lcn2initvals24, in brcms_ucode_data_init()
65 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0absinitvals16, in brcms_ucode_data_init()
68 rc : brcms_ucode_init_buf(wl, (void **)&ucode->d11n0bsinitvals16, in brcms_ucode_data_init()
71 rc : brcms_ucode_init_buf(wl, (void **)&ucode in brcms_ucode_data_init()
94 brcms_ucode_data_free(struct brcms_ucode * ucode) brcms_ucode_data_free() argument
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H A Ducode_loader.h46 int brcms_ucode_data_init(struct brcms_info *wl, struct brcms_ucode *ucode);
48 void brcms_ucode_data_free(struct brcms_ucode *ucode);
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ucode.c70 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_mc_hdr()
105 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_smc_hdr()
132 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gfx_hdr()
291 DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor); in amdgpu_ucode_print_rlc_hdr()
295 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_rlc_hdr()
340 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", in amdgpu_ucode_print_sdma_hdr()
487 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", in amdgpu_ucode_print_psp_hdr()
509 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); in amdgpu_ucode_print_gpu_info_hdr()
826 struct amdgpu_firmware_info *ucode, in amdgpu_ucode_init_single_fw() argument
842 if (!ucode in amdgpu_ucode_init_single_fw()
1090 amdgpu_ucode_patch_jt(struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr) amdgpu_ucode_patch_jt() argument
1145 struct amdgpu_firmware_info *ucode = NULL; amdgpu_ucode_init_bo() local
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H A Damdgpu_cgs.c213 struct amdgpu_firmware_info *ucode; in amdgpu_cgs_get_firmware_info() local
219 ucode = &adev->firmware.ucode[id]; in amdgpu_cgs_get_firmware_info()
220 if (ucode->fw == NULL) in amdgpu_cgs_get_firmware_info()
223 gpu_addr = ucode->mc_addr; in amdgpu_cgs_get_firmware_info()
224 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_cgs_get_firmware_info()
233 info->kptr = ucode->kaddr; in amdgpu_cgs_get_firmware_info()
251 struct amdgpu_firmware_info *ucode = NULL; in amdgpu_cgs_get_firmware_info() local
366 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SM in amdgpu_cgs_get_firmware_info()
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H A Damdgpu_rlc.c332 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; in amdgpu_gfx_rlc_init_microcode_v2_0()
368 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; in amdgpu_gfx_rlc_init_microcode_v2_1()
376 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
384 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; in amdgpu_gfx_rlc_init_microcode_v2_1()
406 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
414 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM]; in amdgpu_gfx_rlc_init_microcode_v2_2()
441 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_P]; in amdgpu_gfx_rlc_init_microcode_v2_3()
449 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_V]; in amdgpu_gfx_rlc_init_microcode_v2_3()
477 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS]; in amdgpu_gfx_rlc_init_microcode_v2_4()
485 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAY in amdgpu_gfx_rlc_init_microcode_v2_4()
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H A Dsmu_v13_0_10.c144 struct amdgpu_firmware_info *ucode; in smu_v13_0_10_mode2_restore_ip() local
149 ucode = &adev->firmware.ucode[i]; in smu_v13_0_10_mode2_restore_ip()
151 switch (ucode->ucode_id) { in smu_v13_0_10_mode2_restore_ip()
154 ucode_list[ucode_count++] = ucode; in smu_v13_0_10_mode2_restore_ip()
163 dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n"); in smu_v13_0_10_mode2_restore_ip()
H A Daldebaran.c215 struct amdgpu_firmware_info *ucode; in aldebaran_mode2_restore_ip() local
223 ucode = &adev->firmware.ucode[i]; in aldebaran_mode2_restore_ip()
224 if (!ucode->fw) in aldebaran_mode2_restore_ip()
226 switch (ucode->ucode_id) { in aldebaran_mode2_restore_ip()
241 ucode_list[ucode_count++] = ucode; in aldebaran_mode2_restore_ip()
282 dev_err(adev->dev, "GFX ucode load failed after reset\n"); in aldebaran_mode2_restore_ip()
H A Damdgpu_psp.c690 struct amdgpu_firmware_info *ucode, in psp_cmd_submit_buf() argument
743 if (ucode) in psp_cmd_submit_buf()
745 "failed to load ucode %s(0x%X) ", in psp_cmd_submit_buf()
746 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); in psp_cmd_submit_buf()
758 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { in psp_cmd_submit_buf()
764 if (ucode) { in psp_cmd_submit_buf()
765 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; in psp_cmd_submit_buf()
766 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; in psp_cmd_submit_buf()
1907 dev_info(adev->dev, "RAS: optional ras ta ucode i in psp_ras_initialize()
2607 psp_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type) psp_get_fw_type() argument
2828 psp_print_fw_hdr(struct psp_context * psp,struct amdgpu_firmware_info * ucode) psp_print_fw_hdr() argument
2876 psp_prep_load_ip_fw_cmd_buf(struct psp_context * psp,struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd) psp_prep_load_ip_fw_cmd_buf() argument
2895 psp_execute_ip_fw_load(struct psp_context * psp,struct amdgpu_firmware_info * ucode) psp_execute_ip_fw_load() argument
2915 struct amdgpu_firmware_info *ucode = psp_load_p2s_table() local
2942 struct amdgpu_firmware_info *ucode = psp_load_smu_fw() local
2974 fw_load_skip_check(struct psp_context * psp,struct amdgpu_firmware_info * ucode) fw_load_skip_check() argument
3005 struct amdgpu_firmware_info *ucode; psp_load_fw_list() local
3020 struct amdgpu_firmware_info *ucode; psp_load_non_psp_fw() local
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/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_ucode.c98 static void set_ucode_filename(struct otx_cpt_ucode *ucode, in set_ucode_filename() argument
101 strscpy(ucode->filename, filename, OTX_CPT_UCODE_NAME_LENGTH); in set_ucode_filename()
189 eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].align_dma; in cpt_set_ucode_base()
191 dma_addr = eng_grp->ucode[0].align_dma; in cpt_set_ucode_base()
326 set_ucode_filename(&tar_info->ucode, filename); in process_tar_file()
327 memcpy(tar_info->ucode.ver_str, ucode_hdr->ver_str, in process_tar_file()
329 tar_info->ucode.ver_num = ucode_hdr->ver_num; in process_tar_file()
330 tar_info->ucode.type = ucode_type; in process_tar_file()
331 tar_info->ucode.size = ucode_size; in process_tar_file()
360 if (!is_eng_type(curr->ucode in get_uc_from_tar_archive()
503 otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode * ucode,int eng_type) otx_cpt_uc_supports_eng_type() argument
560 print_ucode_dbg_info(struct otx_cpt_ucode * ucode) print_ucode_dbg_info() argument
831 ucode_unload(struct device * dev,struct otx_cpt_ucode * ucode) ucode_unload() argument
850 copy_ucode_to_dma_mem(struct device * dev,struct otx_cpt_ucode * ucode,const u8 * ucode_data) copy_ucode_to_dma_mem() argument
880 ucode_load(struct device * dev,struct otx_cpt_ucode * ucode,const char * ucode_filename) ucode_load() argument
1194 struct otx_cpt_ucode *ucode; update_ucode_ptrs() local
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H A Dotx_cptpf_mbox.c140 struct otx_cpt_ucode *ucode; in otx_cpt_bind_vq_to_grp() local
165 ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; in otx_cpt_bind_vq_to_grp()
167 ucode = &eng_grp->ucode[0]; in otx_cpt_bind_vq_to_grp()
169 if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_SE_TYPES)) in otx_cpt_bind_vq_to_grp()
171 else if (otx_cpt_uc_supports_eng_type(ucode, OTX_CPT_AE_TYPES)) in otx_cpt_bind_vq_to_grp()
H A Dotx_cptpf_ucode.h19 /* CPT ucode name maximum length */
30 /* CPT ucode alignment */
33 /* CPT ucode signature size */
83 * ucode version in readable format
85 struct otx_cpt_ucode_ver_num ver_num;/* ucode version number */
86 char filename[OTX_CPT_UCODE_NAME_LENGTH]; /* ucode filename */
87 dma_addr_t dma; /* phys address of ucode image */
88 dma_addr_t align_dma; /* aligned phys address of ucode image */
89 void *va; /* virt address of ucode image */
90 void *align_va; /* aligned virt address of ucode imag
97 struct otx_cpt_ucode ucode;/* microcode information */ global() member
115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */ global() member
141 struct otx_cpt_ucode ucode[OTX_CPT_MAX_ETYPES_PER_GRP]; global() member
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/linux/Documentation/gpu/nova/core/
H A Dfalcon.rst6 The following sections describe the Falcon core and the ucode running on it.
18 The code running on the Falcon cores is also called 'ucode', and will be
33 HS ucode is the most trusted code and has access to pretty much everything on
38 (Write Protect Region), has to be done by the HS ucode and cannot be done by the
39 host CPU or LS ucode.
43 These modes are less secure than HS. Like HS, the LS or NS ucode binary also
47 ucode in HS mode on the SEC2 Falcon, which then authenticates and runs the
60 After nova-core driver reads the necessary ucode from VBIOS, it programs the
61 BROM and DMA registers to trigger the Falcon to load the HS ucode from the system
62 memory into the Falcon's IMEM/DMEM. Once the HS ucode i
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H A Dfwsec.rst15 before loading various ucode images onto other microcontrollers on the GPU,
21 reset and loading them with other non-FWSEC ucode). The kernel driver only needs
26 data required for power management. Once setup, only HS mode ucode can access it
30 various ucode images (also known as applications) -- one of them being FWSEC. For how
33 The Falcon data for each ucode images (including the FWSEC image) is a combination
35 ucode images are stored in the same ROM partition and the PMU table is used to look
H A Dvbios.rst14 are the ones that contain Falcon ucode and what we are mainly looking for.
29 of different functions. The FWSEC ucode is run in heavy-secure mode and
34 loads (see devinit.rst). The DEVINIT ucode is itself another ucode that is
42 region is only accessible to heavy-secure ucode.
173 used to find the required Falcon ucode based on an application ID.
/linux/drivers/soc/fsl/qe/
H A Dqe.c406 const struct qe_microcode *ucode) in qe_upload_microcode() argument
408 const __be32 *code = base + be32_to_cpu(ucode->code_offset); in qe_upload_microcode()
411 if (ucode->major || ucode->minor || ucode->revision) in qe_upload_microcode()
414 ucode->id, ucode->major, ucode->minor, ucode->revision); in qe_upload_microcode()
417 "uploading microcode '%s'\n", ucode in qe_upload_microcode()
535 const struct qe_microcode *ucode = &firmware->microcode[i]; qe_upload_firmware() local
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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_main.c52 * struct ucode - Firmware Header
59 struct ucode { struct
113 struct ucode *ucode; in nitrox_load_fw() local
131 ucode = (struct ucode *)fw->data; in nitrox_load_fw()
133 ucode_size = be32_to_cpu(ucode->code_size) * 2; in nitrox_load_fw()
135 dev_err(DEV(ndev), "Invalid ucode size: %u for firmware %s\n", in nitrox_load_fw()
140 ucode_data = ucode->code; in nitrox_load_fw()
143 memcpy(&ndev->hw.fw_name[0][0], ucode in nitrox_load_fw()
70 codeucode write_to_ucd_unit() argument
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/linux/Documentation/arch/x86/
H A Dmicrocode.rst72 if [ -d /lib/firmware/amd-ucode ]; then
73 cat /lib/firmware/amd-ucode/microcode_amd*.bin > $DSTDIR/AuthenticAMD.bin
76 if [ -d /lib/firmware/intel-ucode ]; then
77 cat /lib/firmware/intel-ucode/* > $DSTDIR/GenuineIntel.bin
80 find . | cpio -o -H newc >../ucode.cpio
83 cat ucode.cpio $INITRD.orig > $INITRD
104 /lib/firmware/{intel-ucode,amd-ucode}. The default distro installation
220 CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15
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H A Dtsx_async_abort.rst46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
71 0 1 0 HW default No Need ucode update Need ucode update
86 0 1 0 HW default No Need ucode update Need ucode update
101 0 1 0 HW default No Need ucode update Need ucode update
/linux/drivers/gpu/nova-core/firmware/
H A Dfwsec.rs11 //! - The ucode signature, so the GSP falcon can run FWSEC in HS mode.
202 ucode: FirmwareDmaObject<Self, Signed>, field
246 &self.ucode.0 in deref()
257 let ucode = bios.fwsec_image().ucode(dev, desc)?; in new_fwsec() localVariable
258 let mut dma_object = DmaObject::from_data(dev, ucode)?; in new_fwsec()
395 ucode: ucode_signed, in new()
/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-drv.c49 * @firmware_name: composite filename of ucode file to load
365 snprintf(drv->firmware_name, sizeof(drv->firmware_name), "%s-%d.ucode", in iwl_request_firmware()
585 const struct iwl_ucode_header *ucode = (const void *)ucode_raw->data; in iwl_parse_v1_v2_firmware() local
590 drv->fw.ucode_ver = le32_to_cpu(ucode->ver); in iwl_parse_v1_v2_firmware()
600 build = le32_to_cpu(ucode->u.v2.build); in iwl_parse_v1_v2_firmware()
602 le32_to_cpu(ucode->u.v2.inst_size)); in iwl_parse_v1_v2_firmware()
604 le32_to_cpu(ucode->u.v2.data_size)); in iwl_parse_v1_v2_firmware()
606 le32_to_cpu(ucode->u.v2.init_size)); in iwl_parse_v1_v2_firmware()
608 le32_to_cpu(ucode->u.v2.init_data_size)); in iwl_parse_v1_v2_firmware()
609 src = ucode in iwl_parse_v1_v2_firmware()
783 const struct iwl_tlv_ucode_header *ucode = (const void *)ucode_raw->data; iwl_parse_tlv_firmware() local
1593 const struct iwl_ucode_header *ucode; iwl_req_fw_callback() local
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv40.h13 u32 *ucode; member
27 u32 *ctxprog = ctx->ucode; in cp_out()
61 u32 *ctxprog = ctx->ucode; in cp_name()
H A Dgf104.c135 .fecs.ucode = &gf100_gr_fecs_ucode,
137 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgf110.c107 .fecs.ucode = &gf100_gr_fecs_ucode,
109 .gpccs.ucode = &gf100_gr_gpccs_ucode,
H A Dgk110b.c126 .fecs.ucode = &gk110_gr_fecs_ucode,
128 .gpccs.ucode = &gk110_gr_gpccs_ucode,
H A Dgf119.c198 .fecs.ucode = &gf100_gr_fecs_ucode,
200 .gpccs.ucode = &gf100_gr_gpccs_ucode,

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