| /linux/drivers/bus/fsl-mc/ ! |
| H A D | fsl-mc-allocator.c | 37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
102 struct fsl_mc_resource_pool *res_pool; fsl_mc_resource_pool_remove_device() local
185 struct fsl_mc_resource_pool *res_pool; fsl_mc_resource_allocate() local
235 struct fsl_mc_resource_pool *res_pool; fsl_mc_resource_free() local
363 struct fsl_mc_resource_pool *res_pool = fsl_mc_populate_irq_pool() local
420 struct fsl_mc_resource_pool *res_pool = fsl_mc_cleanup_irq_pool() local
451 struct fsl_mc_resource_pool *res_pool; fsl_mc_allocate_irqs() local
546 struct fsl_mc_resource_pool *res_pool = fsl_mc_init_all_resource_pools() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/ ! |
| H A D | dcn31_hwseq.c | 94 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
95 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
98 if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerdown) { in enable_memory_low_power()
100 for (i = 0; i < dc->res_pool->stream_enc_count; i++) in enable_memory_low_power()
101 if (dc->res_pool->stream_enc[i]->vpg) in enable_memory_low_power()
102 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
103 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) in enable_memory_low_power()
104 dc->res_pool in enable_memory_low_power()
114 struct resource_pool *res_pool = dc->res_pool; dcn31_init_hw() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn201/ ! |
| H A D | dcn201_hwseq.c | 186 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
187 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
228 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
231 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
232 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
240 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
243 if (res_pool->hubbub) { in dcn201_init_hw()
244 (res_pool in dcn201_init_hw()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ ! |
| H A D | dcn32_hwseq.c | 231 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
243 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_calculate_cab_allocation()
244 num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, mall_ss_size_bytes); in dcn32_calculate_cab_allocation()
353 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
384 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
405 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
445 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
481 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
526 struct mpc *mpc = dc->res_pool->mpc; in dcn32_set_input_transfer_func()
565 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool in dcn32_set_output_transfer_func()
781 struct resource_pool *res_pool = dc->res_pool; dcn32_init_hw() local
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ ! |
| H A D | dcn401_hwseq.c | 88 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn401_program_gamut_remap()
134 struct abm **abms = dc->res_pool->multiple_abms; in dcn401_init_hw()
137 struct resource_pool *res_pool = dc->res_pool; in dcn401_init_hw() local
153 if (res_pool->dccg->funcs->dccg_init) in dcn401_init_hw()
154 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn401_init_hw()
173 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn401_init_hw()
176 if (res_pool->hubbub) { in dcn401_init_hw()
177 (res_pool in dcn401_init_hw()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ ! |
| H A D | dcn10_hwseq.c | 88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
273 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
297 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
442 struct resource_pool *pool = dc->res_pool; in dcn10_log_color_state()
579 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
1001 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
1021 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
1030 for (i = 0; i < dc->res_pool in apply_DEGVIDCN10_253_wa()
1731 struct resource_pool *res_pool = dc->res_pool; dcn10_init_hw() local
3508 get_hubp_by_inst(struct resource_pool * res_pool,int mpcc_inst) get_hubp_by_inst() argument
3522 dcn10_wait_for_mpcc_disconnect(struct dc * dc,struct resource_pool * res_pool,struct pipe_ctx * pipe_ctx) dcn10_wait_for_mpcc_disconnect() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn351/ ! |
| H A D | dcn351_hwseq.c | 45 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_gate()
65 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_calc_blocks_to_ungate()
103 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_down()
108 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { in dcn351_hw_block_power_down()
156 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; in dcn351_hw_block_power_up()
170 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn351_hw_block_power_up()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ ! |
| H A D | dcn314_hwseq.c | 179 struct mpc *mpc = dc->res_pool->mpc; in dcn314_update_odm()
237 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
239 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
240 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
288 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
289 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
290 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
404 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
425 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool in dcn314_resync_fifo_dccg_dio()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ ! |
| H A D | dcn32_resource_helpers.c | 97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
98 return dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes); in dcn32_helper_calculate_num_ways_for_subvp()
113 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
132 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
158 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
175 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
200 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
259 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
274 for (i = 0; i < dc->res_pool->pipe_count; i++) { in override_det_for_subvp()
338 for (j = 0; j < dc->res_pool in dcn32_determine_det_override()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/core/ ! |
| H A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
147 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
168 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
243 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in get_link_enc_used_by_link()
262 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
263 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
301 dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]); in link_enc_cfg_link_encs_assign()
514 link_enc = link->dc->res_pool in link_enc_cfg_get_link_enc_used_by_link()
[all...] |
| H A D | dc.c | 245 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
321 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
322 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
335 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
337 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
339 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
340 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
343 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
344 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
365 if (!dc->res_pool) in destroy_link_encoders()
[all...] |
| H A D | dc_stream.c | 204 if (new_stream->ctx->dc->res_pool->funcs->link_encs_assign && in dc_copy_stream()
298 if (dc->debug.allow_sw_cursor_fallback && dc->res_pool->funcs->get_max_hw_cursor_size) { in dc_stream_check_cursor_attributes()
299 max_cursor_size = dc->res_pool->funcs->get_max_hw_cursor_size(dc, state, stream); in dc_stream_check_cursor_attributes()
448 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_stream_program_cursor_position()
496 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
517 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
529 struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dc_stream_add_writeback()
547 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_fc_disable_writeback()
627 struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst]; in dc_stream_remove_writeback()
796 if (dc->res_pool in dc_stream_add_dsc_to_resource()
[all...] |
| H A D | dc_resource.c | 227 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
232 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
236 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
240 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
245 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
249 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
253 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
257 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
261 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
267 res_pool in dc_create_resource_pool()
[all...] |
| H A D | dc_link_exports.c | 156 return dc->res_pool->oem_device; in dc_get_oem_i2c_device()
163 if (dc->res_pool->oem_device) in dc_is_oem_i2c_device_present()
165 dc->res_pool, in dc_is_oem_i2c_device_present()
166 dc->res_pool->oem_device, in dc_is_oem_i2c_device_present()
182 dc->res_pool, in dc_submit_i2c()
191 struct ddc_service *ddc = dc->res_pool->oem_device; in dc_submit_i2c_oem()
195 dc->res_pool, in dc_submit_i2c_oem()
|
| H A D | dc_surface.c | 73 for (i = 0; i < plane_state->ctx->dc->res_pool->pipe_count; i++) { in dc_plane_get_pipe_mask()
133 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
148 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_get_status()
289 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dc_plane_force_dcc_and_tiling_disable()
|
| H A D | dc_state.c | 298 if (dc->res_pool) in dc_state_construct()
382 if (state->stream_count >= dc->res_pool->timing_generator_count) { in dc_state_add_stream()
392 state, dc->res_pool, stream); in dc_state_add_stream()
417 dc->current_state, dc->res_pool, stream, 1); in dc_state_remove_stream()
419 state, dc->res_pool, stream); in dc_state_remove_stream()
459 new_ctx, cur_ctx, dc->res_pool, in remove_mpc_combine_for_stream()
469 struct resource_pool *pool = dc->res_pool; in dc_state_add_plane()
509 dc->current_state, dc->res_pool, stream, in dc_state_add_plane()
539 struct resource_pool *pool = dc->res_pool; in dc_state_remove_plane()
924 for (i = 0; i < dc->res_pool in dc_state_remove_phantom_streams_and_planes()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/hwss/ ! |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
|
| /linux/drivers/gpu/drm/amd/display/dc/ ! |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
|
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dce110/ ! |
| H A D | dce110_hwseq.c | 215 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1154 struct dccg *dccg = dc->res_pool->dccg; in dce110_disable_stream()
1756 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1757 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1758 dc->res_pool->timing_generators[i]); in power_down_controllers()
1766 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1767 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1770 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
1771 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( in power_down_clock_sources()
1772 dc->res_pool in power_down_clock_sources()
3084 dce110_wait_for_mpcc_disconnect(struct dc * dc,struct resource_pool * res_pool,struct pipe_ctx * pipe_ctx) dce110_wait_for_mpcc_disconnect() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ ! |
| H A D | dcn10_hw_sequencer_debug.c | 81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
85 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
113 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
119 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
191 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
233 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
290 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
330 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
385 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/pg/dcn35/ ! |
| H A D | dcn35_pg_cntl.c | 85 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc && power_on) in pg_cntl35_dsc_pg_control()
86 pg_cntl->ctx->dc->res_pool->dccg->funcs->enable_dsc( in pg_cntl35_dsc_pg_control()
87 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
148 if (pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) { in pg_cntl35_dsc_pg_control()
150 pg_cntl->ctx->dc->res_pool->dccg->funcs->disable_dsc( in pg_cntl35_dsc_pg_control()
151 pg_cntl->ctx->dc->res_pool->dccg, dsc_inst); in pg_cntl35_dsc_pg_control()
411 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
443 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_plane_otg_pg_control()
486 for (i = 0; i < pg_cntl->ctx->dc->res_pool->pipe_count; i++) { in pg_cntl35_init_pg_status()
496 for (i = 0; i < pg_cntl->ctx->dc->res_pool in pg_cntl35_init_pg_status()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn21/ ! |
| H A D | dcn21_hwseq.c | 83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
184 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
217 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
260 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
293 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
|
| /linux/drivers/gpu/drm/amd/display/dc/link/protocols/ ! |
| H A D | link_edp_panel_control.c | 588 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
589 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
636 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
637 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
719 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
720 psr = dc->res_pool->psr; in edp_setup_psr()
820 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
895 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
910 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
924 struct dmub_replay *replay = dc->res_pool in edp_set_replay_allow_active()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/link/ ! |
| H A D | link_factory.c | 395 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
396 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
500 if (link->dc->res_pool->funcs->link_init) in construct_phy()
501 link->dc->res_pool->funcs->link_init(link); in construct_phy()
623 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
637 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
638 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
642 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
649 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
811 if (link->dc->res_pool in construct_dpia()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ ! |
| H A D | dcn31_fpu.c | 522 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
537 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
572 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
576 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
603 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
604 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
675 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
676 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
742 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
743 dcn3_16_ip.max_num_dpp = dc->res_pool in dcn316_update_bw_bounding_box()
[all...] |