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Searched refs:regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_5_0_offset.h14806 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX global() macro
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H A Ddcn_3_6_0_offset.h6993 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 macro
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H A Ddcn_3_2_1_offset.h6541 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 macro
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H A Ddcn_3_5_1_offset.h14785 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX global() macro
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H A Ddcn_4_1_0_offset.h7257 #define regMPCC_MCM2_MPCC_MCM_MEM_PWR_CTRL_BASE_IDX 3 macro
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