Home
last modified time | relevance | path

Searched refs:refcyc_per_meta_chunk_vblank_l (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml_display_rq_dlg_calc.c260 dml_float_t refcyc_per_meta_chunk_vblank_l; in dml_rq_dlg_get_dlg_reg() local
449 refcyc_per_meta_chunk_vblank_l = dml_get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz; in dml_rq_dlg_get_dlg_reg()
466 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (dml_uint_t)(refcyc_per_meta_chunk_vblank_l); in dml_rq_dlg_get_dlg_reg()
549 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_reg()
H A Ddisplay_mode_util.c269 dml_print("DML: refcyc_per_meta_chunk_vblank_l = 0x%x\n", dlg_regs->refcyc_per_meta_chunk_vblank_l); in dml_print_dlg_regs_st()
H A Ddml2_translation_helper.c1473 out->dlg_regs.refcyc_per_meta_chunk_vblank_l = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; in dml2_update_pipe_ctx_dchub_regs()
H A Ddisplay_mode_core_structs.h1948 dml_uint_t refcyc_per_meta_chunk_vblank_l; member
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_rq_dlg_calc_32.c261 double refcyc_per_meta_chunk_vblank_l; in dml32_rq_dlg_get_dlg_reg() local
495 refcyc_per_meta_chunk_vblank_l = get_refcyc_per_meta_chunk_vblank_l_in_us(mode_lib, e2e_pipe_param, in dml32_rq_dlg_get_dlg_reg()
516 dlg_regs->refcyc_per_meta_chunk_vblank_l = refcyc_per_meta_chunk_vblank_l; in dml32_rq_dlg_get_dlg_reg()
601 ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml32_rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn21/
H A Ddcn21_hubp.c424 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
470 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp21_validate_dml_output()
472 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp21_validate_dml_output()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn20/
H A Ddcn20_hubp.c269 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_setup_interdependent()
1190 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp2_read_state_common()
1533 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
1579 if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l) in hubp2_validate_dml_output()
1581 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l); in hubp2_validate_dml_output()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_dchub_registers.h52 uint32_t refcyc_per_meta_chunk_vblank_l; member
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_rq_dlg_helpers.c233 "DML_RQ_DLG_CALC: refcyc_per_meta_chunk_vblank_l = 0x%0x\n", in print__dlg_regs_st()
234 dlg_regs->refcyc_per_meta_chunk_vblank_l); in print__dlg_regs_st()
H A Ddisplay_mode_structs.h639 unsigned int refcyc_per_meta_chunk_vblank_l; member
H A Ddml1_display_rq_dlg_calc.c1539 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml1_rq_dlg_get_dlg_params()
1542 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml1_rq_dlg_get_dlg_params()
1545 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now */ in dml1_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_rq_dlg_calc_20.c1402 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml20_rq_dlg_get_dlg_params()
1405 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); in dml20_rq_dlg_get_dlg_params()
1408 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now in dml20_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_rq_dlg_calc_30.c1579 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = in dml_rq_dlg_get_dlg_params()
1582 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1585 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_rq_dlg_calc_31.c1426 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); in dml_rq_dlg_get_dlg_params()
1427 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1429 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn401/
H A Ddcn401_hubp.c345 REFCYC_PER_META_CHUNK_VBLANK_L, pipe_regs->dlg_regs.refcyc_per_meta_chunk_vblank_l); in hubp401_setup_interdependent()
853 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp401_read_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_rq_dlg_calc_314.c1514 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); in dml_rq_dlg_get_dlg_params()
1515 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); in dml_rq_dlg_get_dlg_params()
1517 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now in dml_rq_dlg_get_dlg_params()
/linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/
H A Ddcn10_hubp.c728 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_setup_interdependent()
959 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l); in hubp1_read_state_common()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer_debug.c266 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_get_dlg_states()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c2580 || (old_dlg_regs.refcyc_per_meta_chunk_vblank_l != new_dlg_regs->refcyc_per_meta_chunk_vblank_l) in dcn401_detect_pipe_changes()
2598 old_dlg_regs.refcyc_per_meta_chunk_vblank_l = new_dlg_regs->refcyc_per_meta_chunk_vblank_l; in dcn401_detect_pipe_changes()
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h1634 double refcyc_per_meta_chunk_vblank_l; member
H A Ddml2_core_dcn4_calcs.c12573 l->refcyc_per_meta_chunk_vblank_l = mode_lib->mp.TimePerMetaChunkVBlank[mode_lib->mp.pipe_plane[pipe_idx]] * l->refclk_freq_in_mhz; in rq_dlg_get_dlg_reg()
12582 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int)(l->refcyc_per_meta_chunk_vblank_l); in rq_dlg_get_dlg_reg()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c402 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l, in dcn10_log_hubp_states()