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Searched refs:ras (Results 1 – 25 of 70) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
35 dev_err(adev->dev, "Failed to register mmhub ras block!\n"); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras in amdgpu_mmhub_ras_sw_init()
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H A Damdgpu_umc.c109 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
111 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_handle_bad_pages()
113 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
114 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
132 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_handle_bad_pages()
136 if (adev->umc.ras && in amdgpu_umc_handle_bad_pages()
137 adev->umc.ras in amdgpu_umc_handle_bad_pages()
287 struct amdgpu_umc_ras *ras; amdgpu_umc_ras_sw_init() local
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H A Damdgpu_hdp.c30 struct amdgpu_hdp_ras *ras; in amdgpu_hdp_ras_sw_init() local
32 if (!adev->hdp.ras) in amdgpu_hdp_ras_sw_init()
35 ras = adev->hdp.ras; in amdgpu_hdp_ras_sw_init()
36 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_hdp_ras_sw_init()
38 dev_err(adev->dev, "Failed to register hdp ras block!\n"); in amdgpu_hdp_ras_sw_init()
42 strcpy(ras->ras_block.ras_comm.name, "hdp"); in amdgpu_hdp_ras_sw_init()
43 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_sw_init()
44 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_sw_init()
45 adev->hdp.ras_if = &ras in amdgpu_hdp_ras_sw_init()
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H A Damdgpu_ras.c50 static const char *RAS_FS_NAME = "ras";
91 /* ras block link */
205 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); in amdgpu_reserve_page_direct()
435 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
436 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
437 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
461 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
462 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
463 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
467 * To check disable/enable, see "ras" feature
1021 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_get_ecc_info() local
2611 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_in_recovery() local
2635 struct amdgpu_ras *ras = amdgpu_ras_do_recovery() local
3320 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_poison_creation_handler() local
3917 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_event_mgr_init() local
4409 struct amdgpu_ras *ras; amdgpu_ras_get_fed_status() local
4420 struct amdgpu_ras *ras; amdgpu_ras_set_fed() local
4433 struct amdgpu_ras *ras; amdgpu_ras_clear_err_state() local
4445 struct amdgpu_ras *ras; amdgpu_ras_set_err_poison() local
4454 struct amdgpu_ras *ras; amdgpu_ras_is_err_state() local
4471 struct amdgpu_ras *ras; __get_ras_event_mgr() local
4540 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_global_ras_isr() local
4710 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_is_supported() local
4738 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_reset_gpu() local
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H A Damdgpu_jpeg.c314 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
316 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
319 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
320 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
322 dev_err(adev->dev, "Failed to register jpeg ras block!\n"); in amdgpu_jpeg_ras_sw_init()
326 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
327 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
328 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
329 adev->jpeg.ras_if = &ras in amdgpu_jpeg_ras_sw_init()
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H A Daldebaran.c377 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
378 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
379 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
380 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
387 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
388 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
389 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
390 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 ecc_ce_cnt = ras->umc_ecc.ecc[eccinfo_table_idx].ce_count_lo_chip; in umc_v8_10_ecc_info_query_correctable_error_count()
360 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
368 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
408 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
415 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
428 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Damdgpu_virt.c236 * amdgpu_virt_rcvd_ras_interrupt() - receive ras interrupt
380 * 1) a ras bad page has been allocated (used by someone); in amdgpu_virt_ras_reserve_bps()
381 * 2) a ras bad page has been reserved (duplicate error injection in amdgpu_virt_ras_reserve_bps()
829 ratelimit_state_init(&adev->virt.ras.ras_error_cnt_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
830 ratelimit_state_init(&adev->virt.ras.ras_cper_dump_rs, 5 * HZ, 1); in amdgpu_virt_init_ras()
832 ratelimit_set_flags(&adev->virt.ras.ras_error_cnt_rs, in amdgpu_virt_init_ras()
834 ratelimit_set_flags(&adev->virt.ras.ras_cper_dump_rs, in amdgpu_virt_init_ras()
837 mutex_init(&adev->virt.ras.ras_telemetry_mutex); in amdgpu_virt_init_ras()
839 adev->virt.ras.cper_rptr = 0; in amdgpu_virt_init_ras()
1329 /* Host allows 15 ras telemetr in amdgpu_virt_req_ras_err_count_internal()
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H A Damdgpu_gfx.c958 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init() local
960 /* adev->gfx.ras is NULL, which means gfx does not in amdgpu_gfx_ras_sw_init()
961 * support ras function, then do nothing here. in amdgpu_gfx_ras_sw_init()
963 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
966 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
968 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
970 dev_err(adev->dev, "Failed to register gfx ras block!\n"); in amdgpu_gfx_ras_sw_init()
974 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
975 ras in amdgpu_gfx_ras_sw_init()
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H A Dgmc_v9_0.c1422 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1431 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1441 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1456 adev->umc.ras = &umc_v12_0_ras; in gmc_v9_0_set_umc_funcs()
1486 adev->mmhub.ras = &mmhub_v1_0_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1489 adev->mmhub.ras = &mmhub_v9_4_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1492 adev->mmhub.ras = &mmhub_v1_7_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1496 adev->mmhub.ras = &mmhub_v1_8_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1499 /* mmhub ras is not available */ in gmc_v9_0_set_mmhub_ras_funcs()
1514 adev->hdp.ras in gmc_v9_0_set_hdp_ras_funcs()
[all...]
H A Dmxgpu_nv.c108 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in xgpu_nv_poll_msg() local
121 ras->is_rma = true; in xgpu_nv_poll_msg()
397 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in xgpu_nv_mailbox_rcv_irq() local
408 ras->is_rma = true; in xgpu_nv_mailbox_rcv_irq()
H A Damdgpu_hdp.h43 struct amdgpu_hdp_ras *ras; member
H A Damdgpu_vcn.c1290 struct amdgpu_vcn_ras *ras; in amdgpu_vcn_ras_sw_init() local
1292 if (!adev->vcn.ras) in amdgpu_vcn_ras_sw_init()
1295 ras = adev->vcn.ras; in amdgpu_vcn_ras_sw_init()
1296 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1298 dev_err(adev->dev, "Failed to register vcn ras block!\n"); in amdgpu_vcn_ras_sw_init()
1302 strcpy(ras->ras_block.ras_comm.name, "vcn"); in amdgpu_vcn_ras_sw_init()
1303 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1304 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_vcn_ras_sw_init()
1305 adev->vcn.ras_if = &ras in amdgpu_vcn_ras_sw_init()
[all...]
H A Damdgpu_mmhub.h71 struct amdgpu_mmhub_ras *ras; member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
86 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/linux/drivers/edac/
H A Di5000_edac.c471 int ras, cas; in i5000_process_fatal_error_info() local
484 ras = NREC_RAS(info->nrecmemb); in i5000_process_fatal_error_info()
487 edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", in i5000_process_fatal_error_info()
489 rdwr ? "Write" : "Read", ras, cas); in i5000_process_fatal_error_info()
525 bank, ras, cas, allErrors, specific); in i5000_process_fatal_error_info()
556 int ras, cas; in i5000_process_nonfatal_error_info() local
579 ras = NREC_RAS(info->nrecmemb); in i5000_process_nonfatal_error_info()
582 edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", in i5000_process_nonfatal_error_info()
584 rdwr ? "Write" : "Read", ras, cas); in i5000_process_nonfatal_error_info()
624 rank, bank, ras, ca in i5000_process_nonfatal_error_info()
[all...]
H A Di5100_edac.c433 unsigned ras, in i5100_handle_ce() argument
440 "bank %u, cas %u, ras %u\n", in i5100_handle_ce()
441 bank, cas, ras); in i5100_handle_ce()
455 unsigned ras, in i5100_handle_ue() argument
462 "bank %u, cas %u, ras %u\n", in i5100_handle_ue()
463 bank, cas, ras); in i5100_handle_ue()
483 unsigned ras; in i5100_read_log() local
503 ras = i5100_recmemb_ras(dw2); in i5100_read_log()
512 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); in i5100_read_log()
525 ras in i5100_read_log()
[all...]
H A Di5400_edac.c524 int ras, cas; in i5400_proccess_non_recoverable_info() local
550 ras = nrec_ras(info); in i5400_proccess_non_recoverable_info()
553 edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", in i5400_proccess_non_recoverable_info()
555 buf_id, rdwr_str(rdwr), ras, cas); in i5400_proccess_non_recoverable_info()
563 bank, buf_id, ras, cas, allErrors, error_name[errnum]); in i5400_proccess_non_recoverable_info()
588 int ras, cas; in i5400_process_nonfatal_error_info() local
620 ras = rec_ras(info); in i5400_process_nonfatal_error_info()
626 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", in i5400_process_nonfatal_error_info()
628 rdwr_str(rdwr), ras, cas); in i5400_process_nonfatal_error_info()
634 branch >> 1, bank, rdwr_str(rdwr), ras, ca in i5400_process_nonfatal_error_info()
[all...]
/linux/net/netfilter/
H A Dnf_conntrack_h323_main.c1625 unsigned char **data, RasMessage *ras) in process_ras() argument
1627 switch (ras->choice) { in process_ras()
1630 &ras->gatekeeperRequest); in process_ras()
1633 &ras->gatekeeperConfirm); in process_ras()
1636 &ras->registrationRequest); in process_ras()
1639 &ras->registrationConfirm); in process_ras()
1642 &ras->unregistrationRequest); in process_ras()
1645 &ras->admissionRequest); in process_ras()
1648 &ras->admissionConfirm); in process_ras()
1651 &ras in process_ras()
1669 static RasMessage ras; ras_help() local
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/linux/drivers/ras/
H A DMakefile2 obj-$(CONFIG_RAS) += ras.o
H A DKconfig34 source "arch/x86/ras/Kconfig"
35 source "drivers/ras/amd/atl/Kconfig"
H A Dras.c10 #include <linux/ras.h>
45 #define TRACE_INCLUDE_PATH ../../include/ras
46 #include <ras/ras_event.h>
86 __setup("ras", parse_ras_param);
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_asn1.h91 int DecodeRasMessage(unsigned char *buf, size_t sz, RasMessage * ras);
/linux/drivers/cxl/core/
H A DMakefile17 cxl_core-y += ras.o

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