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Searched refs:post_div_table (Results 1 – 25 of 52) sorted by relevance

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/linux/drivers/clk/qcom/
H A Dcamcc-sc7280.c86 .post_div_table = post_div_table_cam_cc_pll0_out_even,
109 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
161 .post_div_table = post_div_table_cam_cc_pll1_out_even,
211 .post_div_table = post_div_table_cam_cc_pll2_out_aux,
234 .post_div_table = post_div_table_cam_cc_pll2_out_aux2,
286 .post_div_table = post_div_table_cam_cc_pll3_out_even,
338 .post_div_table = post_div_table_cam_cc_pll4_out_even,
390 .post_div_table = post_div_table_cam_cc_pll5_out_even,
442 .post_div_table = post_div_table_cam_cc_pll6_out_even,
465 .post_div_table
[all...]
H A Dcamcc-sm8550.c100 .post_div_table = post_div_table_cam_cc_pll0_out_even,
123 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
178 .post_div_table = post_div_table_cam_cc_pll1_out_even,
261 .post_div_table = post_div_table_cam_cc_pll3_out_even,
316 .post_div_table = post_div_table_cam_cc_pll4_out_even,
371 .post_div_table = post_div_table_cam_cc_pll5_out_even,
426 .post_div_table = post_div_table_cam_cc_pll6_out_even,
481 .post_div_table = post_div_table_cam_cc_pll7_out_even,
536 .post_div_table = post_div_table_cam_cc_pll8_out_even,
591 .post_div_table
[all...]
H A Dcamcc-sm4450.c85 .post_div_table = post_div_table_cam_cc_pll0_out_even,
108 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
159 .post_div_table = post_div_table_cam_cc_pll1_out_even,
210 .post_div_table = post_div_table_cam_cc_pll2_out_even,
261 .post_div_table = post_div_table_cam_cc_pll3_out_even,
312 .post_div_table = post_div_table_cam_cc_pll4_out_even,
H A Dcamcc-sm8650.c98 .post_div_table = post_div_table_cam_cc_pll0_out_even,
121 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
176 .post_div_table = post_div_table_cam_cc_pll1_out_even,
259 .post_div_table = post_div_table_cam_cc_pll3_out_even,
314 .post_div_table = post_div_table_cam_cc_pll4_out_even,
369 .post_div_table = post_div_table_cam_cc_pll5_out_even,
424 .post_div_table = post_div_table_cam_cc_pll6_out_even,
479 .post_div_table = post_div_table_cam_cc_pll7_out_even,
534 .post_div_table = post_div_table_cam_cc_pll8_out_even,
589 .post_div_table
[all...]
H A Dgpucc-sm6115.c90 .post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
145 .post_div_table = post_div_table_gpu_cc_pll1_out_aux,
H A Dclk-alpha-pll.c1573 if (pll->post_div_table[i].val == val) { in clk_alpha_pll_postdiv_fabia_recalc_rate()
1574 div = pll->post_div_table[i].div; in clk_alpha_pll_postdiv_fabia_recalc_rate()
1596 if (pll->post_div_table[i].val == val) { in clk_trion_pll_postdiv_recalc_rate()
1597 div = pll->post_div_table[i].div; in clk_trion_pll_postdiv_recalc_rate()
1611 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_trion_pll_postdiv_round_rate()
1625 if (pll->post_div_table[i].div == div) { in clk_trion_pll_postdiv_set_rate()
1626 val = pll->post_div_table[i].val; in clk_trion_pll_postdiv_set_rate()
1648 return divider_round_rate(hw, rate, prate, pll->post_div_table, in clk_alpha_pll_postdiv_fabia_round_rate()
1671 if (pll->post_div_table[i].div == div) { in clk_alpha_pll_postdiv_fabia_set_rate()
1672 val = pll->post_div_table[ in clk_alpha_pll_postdiv_fabia_set_rate()
[all...]
H A Dcamcc-milos.c100 .post_div_table = post_div_table_cam_cc_pll0_out_even,
123 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
179 .post_div_table = post_div_table_cam_cc_pll1_out_even,
264 .post_div_table = post_div_table_cam_cc_pll3_out_even,
320 .post_div_table = post_div_table_cam_cc_pll4_out_even,
376 .post_div_table = post_div_table_cam_cc_pll5_out_even,
432 .post_div_table = post_div_table_cam_cc_pll6_out_even,
H A Dlpassaudiocc-sc7280.c106 .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
161 .post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
183 .post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
H A Dcamcc-sm8450.c121 .post_div_table = post_div_table_cam_cc_pll0_out_even,
154 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
227 .post_div_table = post_div_table_cam_cc_pll1_out_even,
334 .post_div_table = post_div_table_cam_cc_pll3_out_even,
407 .post_div_table = post_div_table_cam_cc_pll4_out_even,
480 .post_div_table = post_div_table_cam_cc_pll5_out_even,
553 .post_div_table = post_div_table_cam_cc_pll6_out_even,
626 .post_div_table = post_div_table_cam_cc_pll7_out_even,
699 .post_div_table = post_div_table_cam_cc_pll8_out_even,
H A Dcamcc-sm8150.c89 .post_div_table = post_div_table_cam_cc_pll0_out_even,
112 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
166 .post_div_table = post_div_table_cam_cc_pll1_out_even,
220 .post_div_table = post_div_table_cam_cc_pll2_out_main,
274 .post_div_table = post_div_table_cam_cc_pll3_out_even,
328 .post_div_table = post_div_table_cam_cc_pll4_out_even,
H A Dcamcc-x1e80100.c93 .post_div_table = post_div_table_cam_cc_pll0_out_even,
116 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
171 .post_div_table = post_div_table_cam_cc_pll1_out_even,
254 .post_div_table = post_div_table_cam_cc_pll3_out_even,
309 .post_div_table = post_div_table_cam_cc_pll4_out_even,
364 .post_div_table = post_div_table_cam_cc_pll6_out_even,
419 .post_div_table = post_div_table_cam_cc_pll8_out_even,
H A Dgcc-sm6115.c84 .post_div_table = post_div_table_gpll0_out_aux2,
104 .post_div_table = post_div_table_gpll0_out_main,
154 .post_div_table = post_div_table_gpll10_out_main,
208 .post_div_table = post_div_table_gpll11_out_main,
267 .post_div_table = post_div_table_gpll4_out_main,
306 .post_div_table = post_div_table_gpll6_out_main,
345 .post_div_table = post_div_table_gpll7_out_main,
402 .post_div_table = post_div_table_gpll8_out_main,
454 .post_div_table = post_div_table_gpll9_out_main,
H A Dmmcc-msm8998.c75 .post_div_table = post_div_table_fabia_even,
107 .post_div_table = post_div_table_fabia_even,
135 .post_div_table = post_div_table_fabia_even,
163 .post_div_table = post_div_table_fabia_even,
191 .post_div_table = post_div_table_fabia_even,
219 .post_div_table = post_div_table_fabia_even,
247 .post_div_table = post_div_table_fabia_even,
275 .post_div_table = post_div_table_fabia_even,
H A Dcamcc-sa8775p.c90 .post_div_table = post_div_table_cam_cc_pll0_out_even,
113 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
190 .post_div_table = post_div_table_cam_cc_pll3_out_even,
240 .post_div_table = post_div_table_cam_cc_pll4_out_even,
290 .post_div_table = post_div_table_cam_cc_pll5_out_even,
H A Dclk-alpha-pll.h112 * @post_div_table: table with PLL odd and even post-divider settings
124 const struct clk_div_table *post_div_table; member
H A Dvideocc-sm6350.c75 .post_div_table = post_div_table_video_pll0_out_even,
H A Dcamcc-sdm845.c53 .post_div_table = post_div_table_fabia_even,
85 .post_div_table = post_div_table_fabia_even,
117 .post_div_table = post_div_table_fabia_even,
149 .post_div_table = post_div_table_fabia_even,
H A Dgpucc-msm8998.c79 .post_div_table = post_div_table_fabia_even,
H A Dlpasscorecc-sc7280.c72 .post_div_table = post_div_table_lpass_core_cc_dig_pll_out_odd,
H A Dlpasscorecc-sc7180.c88 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
/linux/drivers/clk/imx/
H A Dclk-imx6sl.c80 static const struct clk_div_table post_div_table[] = { variable
267 hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sl_clocks_init()
269 hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sl_clocks_init()
H A Dclk-imx6sll.c59 static const struct clk_div_table post_div_table[] = { variable
176 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
180 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
H A Dclk-imx6q.c104 static struct clk_div_table post_div_table[] = { variable
467 post_div_table[1].div = 1; in imx6q_clocks_init()
468 post_div_table[2].div = 1; in imx6q_clocks_init()
598 hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6q_clocks_init()
603 hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6q_clocks_init()
H A Dclk-imx6ul.c83 static const struct clk_div_table post_div_table[] = { variable
233 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
237 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
H A Dclk-imx7d.c36 static const struct clk_div_table post_div_table[] = { variable
434 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
438 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()

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