Searched refs:pll_cr_base (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/clk/mvebu/ |
| H A D | ap-cpu-clk.c | 132 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
139 struct regmap *pll_cr_base; member
152 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio); in ap_cpu_clk_recalc_rate()
173 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, ®); in ap_cpu_clk_set_rate()
186 regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg); in ap_cpu_clk_set_rate()
189 regmap_update_bits(clk->pll_cr_base, cpu_force_reg, in ap_cpu_clk_set_rate()
193 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg, in ap_cpu_clk_set_rate()
200 ret = regmap_read_poll_timeout(clk->pll_cr_base, in ap_cpu_clk_set_rate()
207 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg, in ap_cpu_clk_set_rate()
240 pr_err("cannot get pll_cr_base regma in ap_cpu_clock_probe()
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