| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn314/ |
| H A D | dcn314_hwseq.c | 330 unsigned int odm_combine_factor = 0; in dcn314_calculate_dccg_k1_k2_values() local
334 odm_combine_factor = get_odm_config(pipe_ctx, NULL); in dcn314_calculate_dccg_k1_k2_values()
352 if (odm_combine_factor == 2) in dcn314_calculate_dccg_k1_k2_values()
360 return odm_combine_factor; in dcn314_calculate_dccg_k1_k2_values()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/ |
| H A D | dml2_top_soc15.c | 519 unsigned int odm_combine_factor; in dml2_top_mcache_validate_admissability() local
538 num_dpps = odm_combine_factor = params->cfg_support_info->stream_support_info[plane->stream_index].odms_used; in dml2_top_mcache_validate_admissability()
540 if (odm_combine_factor == 1) in dml2_top_mcache_validate_admissability()
545 if (odm_combine_factor > 1) { in dml2_top_mcache_validate_admissability()
547 temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane0.h_ratio * stream->timing.h_active / odm_combine_factor); in dml2_top_mcache_validate_admissability()
553 temp = (unsigned int)math_ceil(plane->composition.scaler_info.plane1.h_ratio * stream->timing.h_active / odm_combine_factor); in dml2_top_mcache_validate_admissability()
582 if (odm_combine_factor > 1) { in dml2_top_mcache_validate_admissability()
583 num_dpps = odm_combine_factor; in dml2_top_mcache_validate_admissability()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml_display_rq_dlg_calc.c | 296 dml_uint_t odm_combine_factor = (odm_mode == dml_odm_mode_combine_2to1 ? 2 : 4); in dml_rq_dlg_get_dlg_reg() local
307 disp_dlg_regs->refcyc_h_blank_end = (dml_uint_t)(((dml_float_t) hblank_end + (dml_float_t) pipe_idx_in_combine * (dml_float_t) hactive / (dml_float_t) odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_reg()
311 dml_print("DML_DLG: %s: odm_combine_factor = %d\n", __func__, odm_combine_factor); in dml_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 338 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); in dml32_rq_dlg_get_dlg_reg() local
342 + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml32_rq_dlg_get_dlg_reg()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_spl_translate.c | 127 spl_in->basic_out.odm_combine_factor = 0; in translate_SPL_in_params_from_pipe_ctx()
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| /linux/drivers/gpu/drm/amd/display/dc/sspl/ |
| H A D | dc_spl_types.h | 472 int odm_combine_factor; // deprecated member
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| H A D | dc_spl.c | 241 int odm_slice_count = spl_in->basic_out.odm_combine_factor; in calculate_odm_slice_in_timing_active()
249 if (spl_in->basic_out.odm_combine_factor > 0) { in calculate_odm_slice_in_timing_active()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| H A D | dcn32_hwseq.c | 1184 unsigned int odm_combine_factor = 0; in dcn32_calculate_dccg_k1_k2_values() local
1189 odm_combine_factor = get_odm_config(pipe_ctx, NULL); in dcn32_calculate_dccg_k1_k2_values()
1207 if ((odm_combine_factor == 2) || (hws->funcs.is_dp_dig_pixel_rate_div_policy && in dcn32_calculate_dccg_k1_k2_values()
1216 return odm_combine_factor; in dcn32_calculate_dccg_k1_k2_values()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 1212 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 in dml_rq_dlg_get_dlg_params() local
1214 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.c | 1086 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 in dml_rq_dlg_get_dlg_params() local
1088 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.c | 1173 unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 in dml_rq_dlg_get_dlg_params() local
1176 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) (((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); in dml_rq_dlg_get_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_shared_types.h | 1586 unsigned int odm_combine_factor; member
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| H A D | dml2_core_dcn4_calcs.c | 12410 l->odm_combine_factor = 2; in rq_dlg_get_dlg_reg()
12413 l->odm_combine_factor = 3; in rq_dlg_get_dlg_reg()
12415 l->odm_combine_factor = 4; in rq_dlg_get_dlg_reg()
12426 disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double)l->hblank_end + (double)l->pipe_idx_in_combine * (double)l->hactive / (double)l->odm_combine_factor) * l->ref_freq_to_pix_freq); in rq_dlg_get_dlg_reg()
12430 DML_LOG_VERBOSE("DML_DLG: %s: odm_combine_factor = %d\n", __func__, l->odm_combine_factor); in rq_dlg_get_dlg_reg()
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