1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6
7 #include <linux/arm-smccc.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/hdmi.h>
11 #include <linux/i2c.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
16 #include <linux/mutex.h>
17 #include <linux/of_platform.h>
18 #include <linux/of.h>
19 #include <linux/of_graph.h>
20 #include <linux/phy/phy.h>
21 #include <linux/platform_device.h>
22 #include <linux/regmap.h>
23
24 #include <sound/hdmi-codec.h>
25
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_bridge.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/drm_print.h>
31 #include <drm/drm_probe_helper.h>
32
33 #include "mtk_cec.h"
34 #include "mtk_hdmi_regs.h"
35
36 #define NCTS_BYTES 7
37
38 enum mtk_hdmi_clk_id {
39 MTK_HDMI_CLK_HDMI_PIXEL,
40 MTK_HDMI_CLK_HDMI_PLL,
41 MTK_HDMI_CLK_AUD_BCLK,
42 MTK_HDMI_CLK_AUD_SPDIF,
43 MTK_HDMI_CLK_COUNT
44 };
45
46 enum hdmi_aud_input_type {
47 HDMI_AUD_INPUT_I2S = 0,
48 HDMI_AUD_INPUT_SPDIF,
49 };
50
51 enum hdmi_aud_i2s_fmt {
52 HDMI_I2S_MODE_RJT_24BIT = 0,
53 HDMI_I2S_MODE_RJT_16BIT,
54 HDMI_I2S_MODE_LJT_24BIT,
55 HDMI_I2S_MODE_LJT_16BIT,
56 HDMI_I2S_MODE_I2S_24BIT,
57 HDMI_I2S_MODE_I2S_16BIT
58 };
59
60 enum hdmi_aud_mclk {
61 HDMI_AUD_MCLK_128FS,
62 HDMI_AUD_MCLK_192FS,
63 HDMI_AUD_MCLK_256FS,
64 HDMI_AUD_MCLK_384FS,
65 HDMI_AUD_MCLK_512FS,
66 HDMI_AUD_MCLK_768FS,
67 HDMI_AUD_MCLK_1152FS,
68 };
69
70 enum hdmi_aud_channel_type {
71 HDMI_AUD_CHAN_TYPE_1_0 = 0,
72 HDMI_AUD_CHAN_TYPE_1_1,
73 HDMI_AUD_CHAN_TYPE_2_0,
74 HDMI_AUD_CHAN_TYPE_2_1,
75 HDMI_AUD_CHAN_TYPE_3_0,
76 HDMI_AUD_CHAN_TYPE_3_1,
77 HDMI_AUD_CHAN_TYPE_4_0,
78 HDMI_AUD_CHAN_TYPE_4_1,
79 HDMI_AUD_CHAN_TYPE_5_0,
80 HDMI_AUD_CHAN_TYPE_5_1,
81 HDMI_AUD_CHAN_TYPE_6_0,
82 HDMI_AUD_CHAN_TYPE_6_1,
83 HDMI_AUD_CHAN_TYPE_7_0,
84 HDMI_AUD_CHAN_TYPE_7_1,
85 HDMI_AUD_CHAN_TYPE_3_0_LRS,
86 HDMI_AUD_CHAN_TYPE_3_1_LRS,
87 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
88 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
89 HDMI_AUD_CHAN_TYPE_6_1_CS,
90 HDMI_AUD_CHAN_TYPE_6_1_CH,
91 HDMI_AUD_CHAN_TYPE_6_1_OH,
92 HDMI_AUD_CHAN_TYPE_6_1_CHR,
93 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
94 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
95 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
96 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
97 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
98 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
99 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
100 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
101 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
102 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
103 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
104 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
105 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
106 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
107 HDMI_AUD_CHAN_TYPE_6_0_CS,
108 HDMI_AUD_CHAN_TYPE_6_0_CH,
109 HDMI_AUD_CHAN_TYPE_6_0_OH,
110 HDMI_AUD_CHAN_TYPE_6_0_CHR,
111 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
112 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
113 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
114 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
115 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
116 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
117 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
118 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
119 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
120 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
121 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
122 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
123 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
124 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
125 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
126 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
127 };
128
129 enum hdmi_aud_channel_swap_type {
130 HDMI_AUD_SWAP_LR,
131 HDMI_AUD_SWAP_LFE_CC,
132 HDMI_AUD_SWAP_LSRS,
133 HDMI_AUD_SWAP_RLS_RRS,
134 HDMI_AUD_SWAP_LR_STATUS,
135 };
136
137 struct hdmi_audio_param {
138 enum hdmi_audio_coding_type aud_codec;
139 enum hdmi_audio_sample_size aud_sample_size;
140 enum hdmi_aud_input_type aud_input_type;
141 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
142 enum hdmi_aud_mclk aud_mclk;
143 enum hdmi_aud_channel_type aud_input_chan_type;
144 struct hdmi_codec_params codec_params;
145 };
146
147 struct mtk_hdmi_conf {
148 bool tz_disabled;
149 bool cea_modes_only;
150 unsigned long max_mode_clock;
151 };
152
153 struct mtk_hdmi {
154 struct drm_bridge bridge;
155 struct drm_bridge *next_bridge;
156 struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
157 struct device *dev;
158 const struct mtk_hdmi_conf *conf;
159 struct phy *phy;
160 struct device *cec_dev;
161 struct i2c_adapter *ddc_adpt;
162 struct clk *clk[MTK_HDMI_CLK_COUNT];
163 struct drm_display_mode mode;
164 bool dvi_mode;
165 struct regmap *sys_regmap;
166 unsigned int sys_offset;
167 struct regmap *regs;
168 struct platform_device *audio_pdev;
169 struct hdmi_audio_param aud_param;
170 bool audio_enable;
171 bool powered;
172 bool enabled;
173 hdmi_codec_plugged_cb plugged_cb;
174 struct device *codec_dev;
175 struct mutex update_plugged_status_lock;
176 };
177
hdmi_ctx_from_bridge(struct drm_bridge * b)178 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
179 {
180 return container_of(b, struct mtk_hdmi, bridge);
181 }
182
mtk_hdmi_hw_vid_black(struct mtk_hdmi * hdmi,bool black)183 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
184 {
185 regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
186 VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH);
187 }
188
mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi * hdmi,bool enable)189 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
190 {
191 struct arm_smccc_res res;
192
193 /*
194 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
195 * output. This bit can only be controlled in ARM supervisor mode.
196 * The ARM trusted firmware provides an API for the HDMI driver to set
197 * this control bit to enable HDMI output in supervisor mode.
198 */
199 if (hdmi->conf && hdmi->conf->tz_disabled)
200 regmap_update_bits(hdmi->sys_regmap,
201 hdmi->sys_offset + HDMI_SYS_CFG20,
202 0x80008005, enable ? 0x80000005 : 0x8000);
203 else
204 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
205 0x80000000, 0, 0, 0, 0, 0, &res);
206
207 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
208 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
209 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
210 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
211 }
212
mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi * hdmi,bool enable)213 static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
214 {
215 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
216 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
217 }
218
mtk_hdmi_hw_aud_mute(struct mtk_hdmi * hdmi)219 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
220 {
221 regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
222 }
223
mtk_hdmi_hw_aud_unmute(struct mtk_hdmi * hdmi)224 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
225 {
226 regmap_clear_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
227 }
228
mtk_hdmi_hw_reset(struct mtk_hdmi * hdmi)229 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
230 {
231 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
232 HDMI_RST, HDMI_RST);
233 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
234 HDMI_RST, 0);
235 regmap_clear_bits(hdmi->regs, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
236 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
237 ANLG_ON, ANLG_ON);
238 }
239
mtk_hdmi_hw_enable_notice(struct mtk_hdmi * hdmi,bool enable_notice)240 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
241 {
242 regmap_update_bits(hdmi->regs, GRL_CFG2, CFG2_NOTICE_EN,
243 enable_notice ? CFG2_NOTICE_EN : 0);
244 }
245
mtk_hdmi_hw_write_int_mask(struct mtk_hdmi * hdmi,u32 int_mask)246 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
247 {
248 regmap_write(hdmi->regs, GRL_INT_MASK, int_mask);
249 }
250
mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi * hdmi,bool enable)251 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
252 {
253 regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0);
254 }
255
mtk_hdmi_hw_send_info_frame(struct mtk_hdmi * hdmi,u8 * buffer,u8 len)256 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
257 u8 len)
258 {
259 u32 ctrl_reg = GRL_CTRL;
260 int i;
261 u8 *frame_data;
262 enum hdmi_infoframe_type frame_type;
263 u8 frame_ver;
264 u8 frame_len;
265 u8 checksum;
266 int ctrl_frame_en = 0;
267
268 frame_type = *buffer++;
269 frame_ver = *buffer++;
270 frame_len = *buffer++;
271 checksum = *buffer++;
272 frame_data = buffer;
273
274 dev_dbg(hdmi->dev,
275 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
276 frame_type, frame_ver, frame_len, checksum);
277
278 switch (frame_type) {
279 case HDMI_INFOFRAME_TYPE_AVI:
280 ctrl_frame_en = CTRL_AVI_EN;
281 ctrl_reg = GRL_CTRL;
282 break;
283 case HDMI_INFOFRAME_TYPE_SPD:
284 ctrl_frame_en = CTRL_SPD_EN;
285 ctrl_reg = GRL_CTRL;
286 break;
287 case HDMI_INFOFRAME_TYPE_AUDIO:
288 ctrl_frame_en = CTRL_AUDIO_EN;
289 ctrl_reg = GRL_CTRL;
290 break;
291 case HDMI_INFOFRAME_TYPE_VENDOR:
292 ctrl_frame_en = VS_EN;
293 ctrl_reg = GRL_ACP_ISRC_CTRL;
294 break;
295 default:
296 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
297 return;
298 }
299 regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
300 regmap_write(hdmi->regs, GRL_INFOFRM_TYPE, frame_type);
301 regmap_write(hdmi->regs, GRL_INFOFRM_VER, frame_ver);
302 regmap_write(hdmi->regs, GRL_INFOFRM_LNG, frame_len);
303
304 regmap_write(hdmi->regs, GRL_IFM_PORT, checksum);
305 for (i = 0; i < frame_len; i++)
306 regmap_write(hdmi->regs, GRL_IFM_PORT, frame_data[i]);
307
308 regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
309 }
310
mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi * hdmi,bool enable)311 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
312 {
313 regmap_update_bits(hdmi->regs, AUDIO_PACKET_OFF,
314 GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF);
315 }
316
mtk_hdmi_hw_config_sys(struct mtk_hdmi * hdmi)317 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
318 {
319 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
320 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
321 usleep_range(2000, 4000);
322 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
323 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
324 }
325
mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi * hdmi)326 static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
327 {
328 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
329 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
330 COLOR_8BIT_MODE);
331 }
332
mtk_hdmi_hw_send_av_mute(struct mtk_hdmi * hdmi)333 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
334 {
335 regmap_clear_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
336 usleep_range(2000, 4000);
337 regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
338 }
339
mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi * hdmi)340 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
341 {
342 regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
343 CFG4_AV_UNMUTE_EN);
344 usleep_range(2000, 4000);
345 regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
346 CFG4_AV_UNMUTE_SET);
347 }
348
mtk_hdmi_hw_ncts_enable(struct mtk_hdmi * hdmi,bool on)349 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
350 {
351 regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, CTS_CTRL_SOFT,
352 on ? 0 : CTS_CTRL_SOFT);
353 }
354
mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi * hdmi,bool enable)355 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
356 bool enable)
357 {
358 regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, NCTS_WRI_ANYTIME,
359 enable ? NCTS_WRI_ANYTIME : 0);
360 }
361
mtk_hdmi_hw_msic_setting(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)362 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
363 struct drm_display_mode *mode)
364 {
365 regmap_clear_bits(hdmi->regs, GRL_CFG4, CFG4_MHL_MODE);
366
367 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
368 mode->clock == 74250 &&
369 mode->vdisplay == 1080)
370 regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
371 else
372 regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
373 }
374
mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi * hdmi,enum hdmi_aud_channel_swap_type swap)375 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
376 enum hdmi_aud_channel_swap_type swap)
377 {
378 u8 swap_bit;
379
380 switch (swap) {
381 case HDMI_AUD_SWAP_LR:
382 swap_bit = LR_SWAP;
383 break;
384 case HDMI_AUD_SWAP_LFE_CC:
385 swap_bit = LFE_CC_SWAP;
386 break;
387 case HDMI_AUD_SWAP_LSRS:
388 swap_bit = LSRS_SWAP;
389 break;
390 case HDMI_AUD_SWAP_RLS_RRS:
391 swap_bit = RLS_RRS_SWAP;
392 break;
393 case HDMI_AUD_SWAP_LR_STATUS:
394 swap_bit = LR_STATUS_SWAP;
395 break;
396 default:
397 swap_bit = LFE_CC_SWAP;
398 break;
399 }
400 regmap_update_bits(hdmi->regs, GRL_CH_SWAP, 0xff, swap_bit);
401 }
402
mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi * hdmi,enum hdmi_audio_sample_size bit_num)403 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
404 enum hdmi_audio_sample_size bit_num)
405 {
406 u32 val;
407
408 switch (bit_num) {
409 case HDMI_AUDIO_SAMPLE_SIZE_16:
410 val = AOUT_16BIT;
411 break;
412 case HDMI_AUDIO_SAMPLE_SIZE_20:
413 val = AOUT_20BIT;
414 break;
415 case HDMI_AUDIO_SAMPLE_SIZE_24:
416 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
417 val = AOUT_24BIT;
418 break;
419 }
420
421 regmap_update_bits(hdmi->regs, GRL_AOUT_CFG, AOUT_BNUM_SEL_MASK, val);
422 }
423
mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi * hdmi,enum hdmi_aud_i2s_fmt i2s_fmt)424 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
425 enum hdmi_aud_i2s_fmt i2s_fmt)
426 {
427 u32 val;
428
429 regmap_read(hdmi->regs, GRL_CFG0, &val);
430 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
431
432 switch (i2s_fmt) {
433 case HDMI_I2S_MODE_RJT_24BIT:
434 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
435 break;
436 case HDMI_I2S_MODE_RJT_16BIT:
437 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
438 break;
439 case HDMI_I2S_MODE_LJT_24BIT:
440 default:
441 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
442 break;
443 case HDMI_I2S_MODE_LJT_16BIT:
444 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
445 break;
446 case HDMI_I2S_MODE_I2S_24BIT:
447 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
448 break;
449 case HDMI_I2S_MODE_I2S_16BIT:
450 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
451 break;
452 }
453 regmap_write(hdmi->regs, GRL_CFG0, val);
454 }
455
mtk_hdmi_hw_audio_config(struct mtk_hdmi * hdmi,bool dst)456 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
457 {
458 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
459 u8 val;
460
461 /* Disable high bitrate, set DST packet normal/double */
462 regmap_clear_bits(hdmi->regs, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
463
464 if (dst)
465 val = DST_NORMAL_DOUBLE | SACD_DST;
466 else
467 val = 0;
468
469 regmap_update_bits(hdmi->regs, GRL_AUDIO_CFG, mask, val);
470 }
471
mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi * hdmi,enum hdmi_aud_channel_type channel_type,u8 channel_count)472 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
473 enum hdmi_aud_channel_type channel_type,
474 u8 channel_count)
475 {
476 unsigned int ch_switch;
477 u8 i2s_uv;
478
479 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
480 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
481 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
482 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
483
484 if (channel_count == 2) {
485 i2s_uv = I2S_UV_CH_EN(0);
486 } else if (channel_count == 3 || channel_count == 4) {
487 if (channel_count == 4 &&
488 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
489 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
490 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
491 else
492 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
493 } else if (channel_count == 6 || channel_count == 5) {
494 if (channel_count == 6 &&
495 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
496 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
497 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
498 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
499 } else {
500 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
501 I2S_UV_CH_EN(0);
502 }
503 } else if (channel_count == 8 || channel_count == 7) {
504 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
505 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
506 } else {
507 i2s_uv = I2S_UV_CH_EN(0);
508 }
509
510 regmap_write(hdmi->regs, GRL_CH_SW0, ch_switch & 0xff);
511 regmap_write(hdmi->regs, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
512 regmap_write(hdmi->regs, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
513 regmap_write(hdmi->regs, GRL_I2S_UV, i2s_uv);
514 }
515
mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi * hdmi,enum hdmi_aud_input_type input_type)516 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
517 enum hdmi_aud_input_type input_type)
518 {
519 u32 val;
520
521 regmap_read(hdmi->regs, GRL_CFG1, &val);
522 if (input_type == HDMI_AUD_INPUT_I2S &&
523 (val & CFG1_SPDIF) == CFG1_SPDIF) {
524 val &= ~CFG1_SPDIF;
525 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
526 (val & CFG1_SPDIF) == 0) {
527 val |= CFG1_SPDIF;
528 }
529 regmap_write(hdmi->regs, GRL_CFG1, val);
530 }
531
mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi * hdmi,u8 * channel_status)532 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
533 u8 *channel_status)
534 {
535 int i;
536
537 for (i = 0; i < 5; i++) {
538 regmap_write(hdmi->regs, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
539 regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, channel_status[i]);
540 regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, channel_status[i]);
541 }
542 for (; i < 24; i++) {
543 regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, 0);
544 regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, 0);
545 }
546 }
547
mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi * hdmi)548 static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
549 {
550 u32 val;
551
552 regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
553 if (val & MIX_CTRL_SRC_EN) {
554 val &= ~MIX_CTRL_SRC_EN;
555 regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
556 usleep_range(255, 512);
557 val |= MIX_CTRL_SRC_EN;
558 regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
559 }
560 }
561
mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi * hdmi)562 static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
563 {
564 u32 val;
565
566 regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
567 val &= ~MIX_CTRL_SRC_EN;
568 regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
569 regmap_write(hdmi->regs, GRL_SHIFT_L1, 0x00);
570 }
571
mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi * hdmi,enum hdmi_aud_mclk mclk)572 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
573 enum hdmi_aud_mclk mclk)
574 {
575 u32 val;
576
577 regmap_read(hdmi->regs, GRL_CFG5, &val);
578 val &= CFG5_CD_RATIO_MASK;
579
580 switch (mclk) {
581 case HDMI_AUD_MCLK_128FS:
582 val |= CFG5_FS128;
583 break;
584 case HDMI_AUD_MCLK_256FS:
585 val |= CFG5_FS256;
586 break;
587 case HDMI_AUD_MCLK_384FS:
588 val |= CFG5_FS384;
589 break;
590 case HDMI_AUD_MCLK_512FS:
591 val |= CFG5_FS512;
592 break;
593 case HDMI_AUD_MCLK_768FS:
594 val |= CFG5_FS768;
595 break;
596 default:
597 val |= CFG5_FS256;
598 break;
599 }
600 regmap_write(hdmi->regs, GRL_CFG5, val);
601 }
602
603 struct hdmi_acr_n {
604 unsigned int clock;
605 unsigned int n[3];
606 };
607
608 /* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
609 static const struct hdmi_acr_n hdmi_rec_n_table[] = {
610 /* Clock, N: 32kHz 44.1kHz 48kHz */
611 { 25175, { 4576, 7007, 6864 } },
612 { 74176, { 11648, 17836, 11648 } },
613 { 148352, { 11648, 8918, 5824 } },
614 { 296703, { 5824, 4459, 5824 } },
615 { 297000, { 3072, 4704, 5120 } },
616 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
617 };
618
619 /**
620 * hdmi_recommended_n() - Return N value recommended by HDMI specification
621 * @freq: audio sample rate in Hz
622 * @clock: rounded TMDS clock in kHz
623 */
hdmi_recommended_n(unsigned int freq,unsigned int clock)624 static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
625 {
626 const struct hdmi_acr_n *recommended;
627 unsigned int i;
628
629 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
630 if (clock == hdmi_rec_n_table[i].clock)
631 break;
632 }
633 recommended = hdmi_rec_n_table + i;
634
635 switch (freq) {
636 case 32000:
637 return recommended->n[0];
638 case 44100:
639 return recommended->n[1];
640 case 48000:
641 return recommended->n[2];
642 case 88200:
643 return recommended->n[1] * 2;
644 case 96000:
645 return recommended->n[2] * 2;
646 case 176400:
647 return recommended->n[1] * 4;
648 case 192000:
649 return recommended->n[2] * 4;
650 default:
651 return (128 * freq) / 1000;
652 }
653 }
654
hdmi_mode_clock_to_hz(unsigned int clock)655 static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
656 {
657 switch (clock) {
658 case 25175:
659 return 25174825; /* 25.2/1.001 MHz */
660 case 74176:
661 return 74175824; /* 74.25/1.001 MHz */
662 case 148352:
663 return 148351648; /* 148.5/1.001 MHz */
664 case 296703:
665 return 296703297; /* 297/1.001 MHz */
666 default:
667 return clock * 1000;
668 }
669 }
670
hdmi_expected_cts(unsigned int audio_sample_rate,unsigned int tmds_clock,unsigned int n)671 static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
672 unsigned int tmds_clock, unsigned int n)
673 {
674 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
675 128 * audio_sample_rate);
676 }
677
mtk_hdmi_get_ncts(unsigned int sample_rate,unsigned int clock,unsigned int * n,unsigned int * cts)678 static void mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
679 unsigned int *n, unsigned int *cts)
680 {
681 *n = hdmi_recommended_n(sample_rate, clock);
682 *cts = hdmi_expected_cts(sample_rate, clock, *n);
683 }
684
do_hdmi_hw_aud_set_ncts(struct mtk_hdmi * hdmi,unsigned int n,unsigned int cts)685 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
686 unsigned int cts)
687 {
688 unsigned char val[NCTS_BYTES];
689 int i;
690
691 regmap_write(hdmi->regs, GRL_NCTS, 0);
692 regmap_write(hdmi->regs, GRL_NCTS, 0);
693 regmap_write(hdmi->regs, GRL_NCTS, 0);
694 memset(val, 0, sizeof(val));
695
696 val[0] = (cts >> 24) & 0xff;
697 val[1] = (cts >> 16) & 0xff;
698 val[2] = (cts >> 8) & 0xff;
699 val[3] = cts & 0xff;
700
701 val[4] = (n >> 16) & 0xff;
702 val[5] = (n >> 8) & 0xff;
703 val[6] = n & 0xff;
704
705 for (i = 0; i < NCTS_BYTES; i++)
706 regmap_write(hdmi->regs, GRL_NCTS, val[i]);
707 }
708
mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi * hdmi,unsigned int sample_rate,unsigned int clock)709 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
710 unsigned int sample_rate,
711 unsigned int clock)
712 {
713 unsigned int n, cts;
714
715 mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
716
717 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
718 __func__, sample_rate, clock, n, cts);
719
720 regmap_update_bits(hdmi->regs, DUMMY_304, AUDIO_I2S_NCTS_SEL, AUDIO_I2S_NCTS_SEL_64);
721 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
722 }
723
mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)724 static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
725 {
726 switch (channel_type) {
727 case HDMI_AUD_CHAN_TYPE_1_0:
728 case HDMI_AUD_CHAN_TYPE_1_1:
729 case HDMI_AUD_CHAN_TYPE_2_0:
730 return 2;
731 case HDMI_AUD_CHAN_TYPE_2_1:
732 case HDMI_AUD_CHAN_TYPE_3_0:
733 return 3;
734 case HDMI_AUD_CHAN_TYPE_3_1:
735 case HDMI_AUD_CHAN_TYPE_4_0:
736 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
737 return 4;
738 case HDMI_AUD_CHAN_TYPE_4_1:
739 case HDMI_AUD_CHAN_TYPE_5_0:
740 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
741 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
742 return 5;
743 case HDMI_AUD_CHAN_TYPE_5_1:
744 case HDMI_AUD_CHAN_TYPE_6_0:
745 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
746 case HDMI_AUD_CHAN_TYPE_6_0_CS:
747 case HDMI_AUD_CHAN_TYPE_6_0_CH:
748 case HDMI_AUD_CHAN_TYPE_6_0_OH:
749 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
750 return 6;
751 case HDMI_AUD_CHAN_TYPE_6_1:
752 case HDMI_AUD_CHAN_TYPE_6_1_CS:
753 case HDMI_AUD_CHAN_TYPE_6_1_CH:
754 case HDMI_AUD_CHAN_TYPE_6_1_OH:
755 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
756 case HDMI_AUD_CHAN_TYPE_7_0:
757 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
758 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
759 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
760 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
761 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
762 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
763 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
764 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
765 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
766 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
767 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
768 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
769 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
770 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
771 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
772 return 7;
773 case HDMI_AUD_CHAN_TYPE_7_1:
774 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
775 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
776 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
777 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
778 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
779 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
780 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
781 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
782 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
783 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
784 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
785 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
786 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
787 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
788 return 8;
789 default:
790 return 2;
791 }
792 }
793
mtk_hdmi_video_change_vpll(struct mtk_hdmi * hdmi,u32 clock)794 static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
795 {
796 unsigned long rate;
797 int ret;
798
799 /* The DPI driver already should have set TVDPLL to the correct rate */
800 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
801 if (ret) {
802 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
803 ret);
804 return ret;
805 }
806
807 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
808
809 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
810 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
811 rate);
812 else
813 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
814
815 mtk_hdmi_hw_config_sys(hdmi);
816 mtk_hdmi_hw_set_deep_color_mode(hdmi);
817 return 0;
818 }
819
mtk_hdmi_video_set_display_mode(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)820 static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
821 struct drm_display_mode *mode)
822 {
823 mtk_hdmi_hw_reset(hdmi);
824 mtk_hdmi_hw_enable_notice(hdmi, true);
825 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
826 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
827 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
828
829 mtk_hdmi_hw_msic_setting(hdmi, mode);
830 }
831
832
mtk_hdmi_aud_set_input(struct mtk_hdmi * hdmi)833 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
834 {
835 enum hdmi_aud_channel_type chan_type;
836 u8 chan_count;
837 bool dst;
838
839 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
840 regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT);
841
842 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
843 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
844 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
845 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
846 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
847 }
848
849 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
850 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
851
852 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
853 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
854 mtk_hdmi_hw_audio_config(hdmi, dst);
855
856 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
857 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
858 else
859 chan_type = hdmi->aud_param.aud_input_chan_type;
860 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
861 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
862 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
863 }
864
mtk_hdmi_aud_set_src(struct mtk_hdmi * hdmi,struct drm_display_mode * display_mode)865 static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
866 struct drm_display_mode *display_mode)
867 {
868 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
869
870 mtk_hdmi_hw_ncts_enable(hdmi, false);
871 mtk_hdmi_hw_aud_src_disable(hdmi);
872 regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_ACLK_INV);
873
874 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
875 switch (sample_rate) {
876 case 32000:
877 case 44100:
878 case 48000:
879 case 88200:
880 case 96000:
881 break;
882 default:
883 return -EINVAL;
884 }
885 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
886 } else {
887 switch (sample_rate) {
888 case 32000:
889 case 44100:
890 case 48000:
891 break;
892 default:
893 return -EINVAL;
894 }
895 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
896 }
897
898 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
899
900 mtk_hdmi_hw_aud_src_reenable(hdmi);
901 return 0;
902 }
903
mtk_hdmi_aud_output_config(struct mtk_hdmi * hdmi,struct drm_display_mode * display_mode)904 static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
905 struct drm_display_mode *display_mode)
906 {
907 mtk_hdmi_hw_aud_mute(hdmi);
908 mtk_hdmi_hw_send_aud_packet(hdmi, false);
909
910 mtk_hdmi_aud_set_input(hdmi);
911 mtk_hdmi_aud_set_src(hdmi, display_mode);
912 mtk_hdmi_hw_aud_set_channel_status(hdmi,
913 hdmi->aud_param.codec_params.iec.status);
914
915 usleep_range(50, 100);
916
917 mtk_hdmi_hw_ncts_enable(hdmi, true);
918 mtk_hdmi_hw_send_aud_packet(hdmi, true);
919 mtk_hdmi_hw_aud_unmute(hdmi);
920 return 0;
921 }
922
mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)923 static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
924 struct drm_display_mode *mode)
925 {
926 struct hdmi_avi_infoframe frame;
927 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
928 ssize_t err;
929
930 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
931 hdmi->curr_conn, mode);
932 if (err < 0) {
933 dev_err(hdmi->dev,
934 "Failed to get AVI infoframe from mode: %zd\n", err);
935 return err;
936 }
937
938 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
939 if (err < 0) {
940 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
941 return err;
942 }
943
944 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
945 return 0;
946 }
947
mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi * hdmi)948 static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi)
949 {
950 struct drm_bridge *bridge = &hdmi->bridge;
951 struct hdmi_spd_infoframe frame;
952 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
953 ssize_t err;
954
955 err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product);
956 if (err < 0) {
957 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
958 err);
959 return err;
960 }
961
962 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
963 if (err < 0) {
964 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
965 return err;
966 }
967
968 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
969 return 0;
970 }
971
mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi * hdmi)972 static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
973 {
974 struct hdmi_audio_infoframe frame;
975 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
976 ssize_t err;
977
978 err = hdmi_audio_infoframe_init(&frame);
979 if (err < 0) {
980 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
981 err);
982 return err;
983 }
984
985 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
986 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
987 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
988 frame.channels = mtk_hdmi_aud_get_chnl_count(
989 hdmi->aud_param.aud_input_chan_type);
990
991 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
992 if (err < 0) {
993 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
994 err);
995 return err;
996 }
997
998 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
999 return 0;
1000 }
1001
mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)1002 static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1003 struct drm_display_mode *mode)
1004 {
1005 struct hdmi_vendor_infoframe frame;
1006 u8 buffer[10];
1007 ssize_t err;
1008
1009 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1010 hdmi->curr_conn, mode);
1011 if (err) {
1012 dev_err(hdmi->dev,
1013 "Failed to get vendor infoframe from mode: %zd\n", err);
1014 return err;
1015 }
1016
1017 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1018 if (err < 0) {
1019 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1020 err);
1021 return err;
1022 }
1023
1024 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1025 return 0;
1026 }
1027
mtk_hdmi_audio_enable(struct mtk_hdmi * hdmi)1028 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1029 {
1030 mtk_hdmi_hw_send_aud_packet(hdmi, true);
1031 hdmi->audio_enable = true;
1032 }
1033
mtk_hdmi_audio_disable(struct mtk_hdmi * hdmi)1034 static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1035 {
1036 mtk_hdmi_hw_send_aud_packet(hdmi, false);
1037 hdmi->audio_enable = false;
1038 }
1039
mtk_hdmi_output_set_display_mode(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)1040 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1041 struct drm_display_mode *mode)
1042 {
1043 int ret;
1044
1045 mtk_hdmi_hw_vid_black(hdmi, true);
1046 mtk_hdmi_hw_aud_mute(hdmi);
1047 mtk_hdmi_hw_send_av_mute(hdmi);
1048 phy_power_off(hdmi->phy);
1049
1050 ret = mtk_hdmi_video_change_vpll(hdmi,
1051 mode->clock * 1000);
1052 if (ret) {
1053 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1054 return ret;
1055 }
1056 mtk_hdmi_video_set_display_mode(hdmi, mode);
1057
1058 phy_power_on(hdmi->phy);
1059 mtk_hdmi_aud_output_config(hdmi, mode);
1060
1061 mtk_hdmi_hw_vid_black(hdmi, false);
1062 mtk_hdmi_hw_aud_unmute(hdmi);
1063 mtk_hdmi_hw_send_av_unmute(hdmi);
1064
1065 return 0;
1066 }
1067
1068 static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1069 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1070 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1071 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1072 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1073 };
1074
mtk_hdmi_get_all_clk(struct mtk_hdmi * hdmi,struct device_node * np)1075 static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1076 struct device_node *np)
1077 {
1078 int i;
1079
1080 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1081 hdmi->clk[i] = of_clk_get_by_name(np,
1082 mtk_hdmi_clk_names[i]);
1083 if (IS_ERR(hdmi->clk[i]))
1084 return PTR_ERR(hdmi->clk[i]);
1085 }
1086 return 0;
1087 }
1088
mtk_hdmi_clk_enable_audio(struct mtk_hdmi * hdmi)1089 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1090 {
1091 int ret;
1092
1093 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1094 if (ret)
1095 return ret;
1096
1097 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1098 if (ret) {
1099 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1100 return ret;
1101 }
1102
1103 return 0;
1104 }
1105
mtk_hdmi_clk_disable_audio(struct mtk_hdmi * hdmi)1106 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1107 {
1108 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1109 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1110 }
1111
1112 static enum drm_connector_status
mtk_hdmi_update_plugged_status(struct mtk_hdmi * hdmi)1113 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1114 {
1115 bool connected;
1116
1117 mutex_lock(&hdmi->update_plugged_status_lock);
1118 connected = mtk_cec_hpd_high(hdmi->cec_dev);
1119 if (hdmi->plugged_cb && hdmi->codec_dev)
1120 hdmi->plugged_cb(hdmi->codec_dev, connected);
1121 mutex_unlock(&hdmi->update_plugged_status_lock);
1122
1123 return connected ?
1124 connector_status_connected : connector_status_disconnected;
1125 }
1126
mtk_hdmi_detect(struct mtk_hdmi * hdmi)1127 static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1128 {
1129 return mtk_hdmi_update_plugged_status(hdmi);
1130 }
1131
1132 static enum drm_mode_status
mtk_hdmi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)1133 mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1134 const struct drm_display_info *info,
1135 const struct drm_display_mode *mode)
1136 {
1137 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1138
1139 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1140 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1141 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1142
1143 if (hdmi->conf) {
1144 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
1145 return MODE_BAD;
1146
1147 if (hdmi->conf->max_mode_clock &&
1148 mode->clock > hdmi->conf->max_mode_clock)
1149 return MODE_CLOCK_HIGH;
1150 }
1151
1152 if (mode->clock < 27000)
1153 return MODE_CLOCK_LOW;
1154 if (mode->clock > 297000)
1155 return MODE_CLOCK_HIGH;
1156
1157 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1158 }
1159
mtk_hdmi_hpd_event(bool hpd,struct device * dev)1160 static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1161 {
1162 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1163
1164 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1165 static enum drm_connector_status status;
1166
1167 status = mtk_hdmi_detect(hdmi);
1168 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1169 drm_bridge_hpd_notify(&hdmi->bridge, status);
1170 }
1171 }
1172
1173 /*
1174 * Bridge callbacks
1175 */
1176
1177 static enum drm_connector_status
mtk_hdmi_bridge_detect(struct drm_bridge * bridge,struct drm_connector * connector)1178 mtk_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
1179 {
1180 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1181
1182 return mtk_hdmi_detect(hdmi);
1183 }
1184
mtk_hdmi_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)1185 static const struct drm_edid *mtk_hdmi_bridge_edid_read(struct drm_bridge *bridge,
1186 struct drm_connector *connector)
1187 {
1188 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1189 const struct drm_edid *drm_edid;
1190
1191 if (!hdmi->ddc_adpt)
1192 return NULL;
1193 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_adpt);
1194 if (drm_edid) {
1195 /*
1196 * FIXME: This should use !connector->display_info.has_audio (or
1197 * !connector->display_info.is_hdmi) from a path that has read
1198 * the EDID and called drm_edid_connector_update().
1199 */
1200 const struct edid *edid = drm_edid_raw(drm_edid);
1201
1202 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1203 }
1204
1205 return drm_edid;
1206 }
1207
mtk_hdmi_bridge_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)1208 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1209 struct drm_encoder *encoder,
1210 enum drm_bridge_attach_flags flags)
1211 {
1212 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1213 int ret;
1214
1215 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1216 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1217 __func__);
1218 return -EINVAL;
1219 }
1220
1221 if (hdmi->next_bridge) {
1222 ret = drm_bridge_attach(encoder, hdmi->next_bridge,
1223 bridge, flags);
1224 if (ret)
1225 return ret;
1226 }
1227
1228 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1229
1230 return 0;
1231 }
1232
mtk_hdmi_bridge_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1233 static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1234 const struct drm_display_mode *mode,
1235 struct drm_display_mode *adjusted_mode)
1236 {
1237 return true;
1238 }
1239
mtk_hdmi_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1240 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1241 struct drm_atomic_state *state)
1242 {
1243 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1244
1245 if (!hdmi->enabled)
1246 return;
1247
1248 phy_power_off(hdmi->phy);
1249 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1250 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1251
1252 hdmi->curr_conn = NULL;
1253
1254 hdmi->enabled = false;
1255 }
1256
mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1257 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1258 struct drm_atomic_state *state)
1259 {
1260 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1261
1262 if (!hdmi->powered)
1263 return;
1264
1265 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1266 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1267
1268 hdmi->powered = false;
1269 }
1270
mtk_hdmi_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)1271 static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1272 const struct drm_display_mode *mode,
1273 const struct drm_display_mode *adjusted_mode)
1274 {
1275 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1276
1277 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1278 adjusted_mode->name, adjusted_mode->hdisplay);
1279 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1280 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1281 adjusted_mode->htotal);
1282 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1283 adjusted_mode->hskew, adjusted_mode->vdisplay);
1284 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1285 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1286 adjusted_mode->vtotal);
1287 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1288 adjusted_mode->vscan, adjusted_mode->flags);
1289
1290 drm_mode_copy(&hdmi->mode, adjusted_mode);
1291 }
1292
mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1293 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1294 struct drm_atomic_state *state)
1295 {
1296 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1297
1298 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1299 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1300
1301 hdmi->powered = true;
1302 }
1303
mtk_hdmi_send_infoframe(struct mtk_hdmi * hdmi,struct drm_display_mode * mode)1304 static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1305 struct drm_display_mode *mode)
1306 {
1307 mtk_hdmi_setup_audio_infoframe(hdmi);
1308 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1309 mtk_hdmi_setup_spd_infoframe(hdmi);
1310 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1311 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1312 }
1313
mtk_hdmi_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1314 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1315 struct drm_atomic_state *state)
1316 {
1317 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1318
1319 /* Retrieve the connector through the atomic state. */
1320 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1321 bridge->encoder);
1322
1323 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1324 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1325 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1326 phy_power_on(hdmi->phy);
1327 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1328
1329 hdmi->enabled = true;
1330 }
1331
1332 static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1333 .mode_valid = mtk_hdmi_bridge_mode_valid,
1334 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1335 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1336 .atomic_reset = drm_atomic_helper_bridge_reset,
1337 .attach = mtk_hdmi_bridge_attach,
1338 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1339 .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1340 .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1341 .mode_set = mtk_hdmi_bridge_mode_set,
1342 .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1343 .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1344 .detect = mtk_hdmi_bridge_detect,
1345 .edid_read = mtk_hdmi_bridge_edid_read,
1346 };
1347
mtk_hdmi_get_cec_dev(struct mtk_hdmi * hdmi,struct device * dev,struct device_node * np)1348 static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
1349 {
1350 struct platform_device *cec_pdev;
1351 struct device_node *cec_np;
1352 int ret;
1353
1354 ret = mtk_hdmi_get_all_clk(hdmi, np);
1355 if (ret)
1356 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1357
1358 /* The CEC module handles HDMI hotplug detection */
1359 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1360 if (!cec_np)
1361 return dev_err_probe(dev, -EINVAL, "Failed to find CEC node\n");
1362
1363 cec_pdev = of_find_device_by_node(cec_np);
1364 if (!cec_pdev) {
1365 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1366 cec_np);
1367 of_node_put(cec_np);
1368 return -EPROBE_DEFER;
1369 }
1370 of_node_put(cec_np);
1371
1372 /*
1373 * The mediatek,syscon-hdmi property contains a phandle link to the
1374 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1375 * registers it contains.
1376 */
1377 hdmi->sys_regmap = syscon_regmap_lookup_by_phandle_args(np, "mediatek,syscon-hdmi",
1378 1, &hdmi->sys_offset);
1379 if (IS_ERR(hdmi->sys_regmap))
1380 return dev_err_probe(dev, PTR_ERR(hdmi->sys_regmap),
1381 "Failed to get system configuration registers\n");
1382
1383 hdmi->cec_dev = &cec_pdev->dev;
1384 return 0;
1385 }
1386
mtk_hdmi_dt_parse_pdata(struct mtk_hdmi * hdmi,struct platform_device * pdev)1387 static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1388 struct platform_device *pdev)
1389 {
1390 struct device *dev = &pdev->dev;
1391 struct device_node *np = dev->of_node;
1392 struct device_node *remote, *i2c_np;
1393 int ret;
1394
1395 ret = mtk_hdmi_get_all_clk(hdmi, np);
1396 if (ret)
1397 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1398
1399 hdmi->regs = device_node_to_regmap(dev->of_node);
1400 if (IS_ERR(hdmi->regs))
1401 return PTR_ERR(hdmi->regs);
1402
1403 remote = of_graph_get_remote_node(np, 1, 0);
1404 if (!remote)
1405 return -EINVAL;
1406
1407 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1408 hdmi->next_bridge = of_drm_find_bridge(remote);
1409 if (!hdmi->next_bridge) {
1410 dev_err(dev, "Waiting for external bridge\n");
1411 of_node_put(remote);
1412 return -EPROBE_DEFER;
1413 }
1414 }
1415
1416 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1417 of_node_put(remote);
1418 if (!i2c_np)
1419 return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
1420
1421 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1422 of_node_put(i2c_np);
1423 if (!hdmi->ddc_adpt)
1424 return dev_err_probe(dev, -EINVAL, "Failed to get ddc i2c adapter by node\n");
1425
1426 ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
1427 if (ret)
1428 return ret;
1429
1430 return 0;
1431 }
1432
1433 /*
1434 * HDMI audio codec callbacks
1435 */
1436
mtk_hdmi_audio_params(struct mtk_hdmi * hdmi,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1437 static int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
1438 struct hdmi_codec_daifmt *daifmt,
1439 struct hdmi_codec_params *params)
1440 {
1441 struct hdmi_audio_param aud_params = { 0 };
1442 unsigned int chan = params->cea.channels;
1443
1444 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1445 params->sample_rate, params->sample_width, chan);
1446
1447 if (!hdmi->bridge.encoder)
1448 return -ENODEV;
1449
1450 switch (chan) {
1451 case 2:
1452 aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1453 break;
1454 case 4:
1455 aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1456 break;
1457 case 6:
1458 aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1459 break;
1460 case 8:
1461 aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1462 break;
1463 default:
1464 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1465 return -EINVAL;
1466 }
1467
1468 switch (params->sample_rate) {
1469 case 32000:
1470 case 44100:
1471 case 48000:
1472 case 88200:
1473 case 96000:
1474 case 176400:
1475 case 192000:
1476 break;
1477 default:
1478 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1479 params->sample_rate);
1480 return -EINVAL;
1481 }
1482
1483 switch (daifmt->fmt) {
1484 case HDMI_I2S:
1485 aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1486 aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1487 aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1488 aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1489 aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1490 break;
1491 case HDMI_SPDIF:
1492 aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1493 aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1494 aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1495 break;
1496 default:
1497 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1498 daifmt->fmt);
1499 return -EINVAL;
1500 }
1501 memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
1502 memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
1503
1504 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1505 aud_params.aud_codec, aud_params.aud_input_type,
1506 aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
1507
1508 return 0;
1509 }
1510
mtk_hdmi_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1511 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1512 struct hdmi_codec_daifmt *daifmt,
1513 struct hdmi_codec_params *params)
1514 {
1515 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1516
1517 if (!hdmi->audio_enable) {
1518 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1519 return -EINVAL;
1520 }
1521
1522 mtk_hdmi_audio_params(hdmi, daifmt, params);
1523 mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1524
1525 return 0;
1526 }
1527
mtk_hdmi_audio_startup(struct device * dev,void * data)1528 static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1529 {
1530 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1531
1532 mtk_hdmi_audio_enable(hdmi);
1533
1534 return 0;
1535 }
1536
mtk_hdmi_audio_shutdown(struct device * dev,void * data)1537 static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1538 {
1539 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1540
1541 mtk_hdmi_audio_disable(hdmi);
1542 }
1543
1544 static int
mtk_hdmi_audio_mute(struct device * dev,void * data,bool enable,int direction)1545 mtk_hdmi_audio_mute(struct device *dev, void *data,
1546 bool enable, int direction)
1547 {
1548 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1549
1550 if (enable)
1551 mtk_hdmi_hw_aud_mute(hdmi);
1552 else
1553 mtk_hdmi_hw_aud_unmute(hdmi);
1554
1555 return 0;
1556 }
1557
mtk_hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)1558 static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1559 {
1560 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1561
1562 if (hdmi->enabled)
1563 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1564 else
1565 memset(buf, 0, len);
1566 return 0;
1567 }
1568
mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi * hdmi,hdmi_codec_plugged_cb fn,struct device * codec_dev)1569 static void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
1570 struct device *codec_dev)
1571 {
1572 mutex_lock(&hdmi->update_plugged_status_lock);
1573 hdmi->plugged_cb = fn;
1574 hdmi->codec_dev = codec_dev;
1575 mutex_unlock(&hdmi->update_plugged_status_lock);
1576 }
1577
mtk_hdmi_audio_hook_plugged_cb(struct device * dev,void * data,hdmi_codec_plugged_cb fn,struct device * codec_dev)1578 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1579 hdmi_codec_plugged_cb fn,
1580 struct device *codec_dev)
1581 {
1582 struct mtk_hdmi *hdmi = data;
1583
1584 mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
1585 mtk_hdmi_update_plugged_status(hdmi);
1586
1587 return 0;
1588 }
1589
1590 static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1591 .hw_params = mtk_hdmi_audio_hw_params,
1592 .audio_startup = mtk_hdmi_audio_startup,
1593 .audio_shutdown = mtk_hdmi_audio_shutdown,
1594 .mute_stream = mtk_hdmi_audio_mute,
1595 .get_eld = mtk_hdmi_audio_get_eld,
1596 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1597 };
1598
mtk_hdmi_unregister_audio_driver(void * data)1599 static void mtk_hdmi_unregister_audio_driver(void *data)
1600 {
1601 platform_device_unregister(data);
1602 }
1603
mtk_hdmi_register_audio_driver(struct device * dev)1604 static int mtk_hdmi_register_audio_driver(struct device *dev)
1605 {
1606 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1607 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1608 struct hdmi_codec_pdata codec_data = {
1609 .ops = &mtk_hdmi_audio_codec_ops,
1610 .max_i2s_channels = 2,
1611 .i2s = 1,
1612 .data = hdmi,
1613 .no_capture_mute = 1,
1614 };
1615 int ret;
1616
1617 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1618 aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1619 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1620 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1621 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1622 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1623
1624 hdmi->audio_pdev = platform_device_register_data(dev,
1625 HDMI_CODEC_DRV_NAME,
1626 PLATFORM_DEVID_AUTO,
1627 &codec_data,
1628 sizeof(codec_data));
1629 if (IS_ERR(hdmi->audio_pdev))
1630 return PTR_ERR(hdmi->audio_pdev);
1631
1632 ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
1633 hdmi->audio_pdev);
1634 if (ret)
1635 return ret;
1636
1637 return 0;
1638 }
1639
mtk_hdmi_probe(struct platform_device * pdev)1640 static int mtk_hdmi_probe(struct platform_device *pdev)
1641 {
1642 struct mtk_hdmi *hdmi;
1643 struct device *dev = &pdev->dev;
1644 int ret;
1645
1646 hdmi = devm_drm_bridge_alloc(dev, struct mtk_hdmi, bridge,
1647 &mtk_hdmi_bridge_funcs);
1648 if (IS_ERR(hdmi))
1649 return PTR_ERR(hdmi);
1650
1651 hdmi->dev = dev;
1652 hdmi->conf = of_device_get_match_data(dev);
1653
1654 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1655 if (ret)
1656 return ret;
1657
1658 hdmi->phy = devm_phy_get(dev, "hdmi");
1659 if (IS_ERR(hdmi->phy))
1660 return dev_err_probe(dev, PTR_ERR(hdmi->phy),
1661 "Failed to get HDMI PHY\n");
1662
1663 mutex_init(&hdmi->update_plugged_status_lock);
1664 platform_set_drvdata(pdev, hdmi);
1665
1666 ret = mtk_hdmi_register_audio_driver(dev);
1667 if (ret)
1668 return dev_err_probe(dev, ret,
1669 "Failed to register audio driver\n");
1670
1671 hdmi->bridge.of_node = pdev->dev.of_node;
1672 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1673 | DRM_BRIDGE_OP_HPD;
1674 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1675 hdmi->bridge.vendor = "MediaTek";
1676 hdmi->bridge.product = "On-Chip HDMI";
1677
1678 ret = devm_drm_bridge_add(dev, &hdmi->bridge);
1679 if (ret)
1680 return dev_err_probe(dev, ret, "Failed to add bridge\n");
1681
1682 ret = mtk_hdmi_clk_enable_audio(hdmi);
1683 if (ret)
1684 return dev_err_probe(dev, ret,
1685 "Failed to enable audio clocks\n");
1686
1687 return 0;
1688 }
1689
mtk_hdmi_remove(struct platform_device * pdev)1690 static void mtk_hdmi_remove(struct platform_device *pdev)
1691 {
1692 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1693
1694 mtk_hdmi_clk_disable_audio(hdmi);
1695 }
1696
mtk_hdmi_suspend(struct device * dev)1697 static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
1698 {
1699 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1700
1701 mtk_hdmi_clk_disable_audio(hdmi);
1702
1703 return 0;
1704 }
1705
mtk_hdmi_resume(struct device * dev)1706 static __maybe_unused int mtk_hdmi_resume(struct device *dev)
1707 {
1708 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1709
1710 return mtk_hdmi_clk_enable_audio(hdmi);
1711 }
1712
1713 static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
1714
1715 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1716 .tz_disabled = true,
1717 };
1718
1719 static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
1720 .max_mode_clock = 148500,
1721 .cea_modes_only = true,
1722 };
1723
1724 static const struct of_device_id mtk_hdmi_of_ids[] = {
1725 { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
1726 { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
1727 { .compatible = "mediatek,mt8173-hdmi" },
1728 { /* sentinel */ }
1729 };
1730 MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
1731
1732 static struct platform_driver mtk_hdmi_driver = {
1733 .probe = mtk_hdmi_probe,
1734 .remove = mtk_hdmi_remove,
1735 .driver = {
1736 .name = "mediatek-drm-hdmi",
1737 .of_match_table = mtk_hdmi_of_ids,
1738 .pm = &mtk_hdmi_pm_ops,
1739 },
1740 };
1741 module_platform_driver(mtk_hdmi_driver);
1742
1743 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1744 MODULE_DESCRIPTION("MediaTek HDMI Driver");
1745 MODULE_LICENSE("GPL v2");
1746 MODULE_IMPORT_NS("DRM_MTK_HDMI_V1");
1747