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Searched refs:mmOTG4_OTG_COUNT_CONTROL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h7220 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_1_0_offset.h8862 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_2_offset.h8774 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_0_0_offset.h9893 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_0_offset.h9636 #define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 macro
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