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Searched refs:mmOTG3_OTG_DRR_CONTROL_BASE_IDX (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h7341 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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H A Ddcn_1_0_offset.h7136 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_1_0_offset.h8778 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_2_offset.h8690 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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H A Ddcn_2_0_0_offset.h9809 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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H A Ddcn_3_0_0_offset.h9550 #define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 macro
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