| /linux/drivers/thermal/renesas/ |
| H A D | rcar_gen3_thermal.c | 80 const struct rcar_gen3_thermal_fuse_info *fuses; member
264 const struct rcar_gen3_thermal_fuse_info *fuses = priv->info->fuses; in rcar_gen3_thermal_fetch_fuses() local
271 priv->ptat[0] = rcar_gen3_thermal_read(priv->tscs[0], fuses->ptat[0]) in rcar_gen3_thermal_fetch_fuses()
272 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
273 priv->ptat[1] = rcar_gen3_thermal_read(priv->tscs[0], fuses->ptat[1]) in rcar_gen3_thermal_fetch_fuses()
274 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
275 priv->ptat[2] = rcar_gen3_thermal_read(priv->tscs[0], fuses->ptat[2]) in rcar_gen3_thermal_fetch_fuses()
276 & fuses->mask; in rcar_gen3_thermal_fetch_fuses()
281 tsc->thcode[0] = rcar_gen3_thermal_read(tsc, fuses in rcar_gen3_thermal_fetch_fuses()
[all...] |
| /linux/drivers/nvmem/ |
| H A D | apple-efuses.c | 15 void __iomem *fuses; member
25 *dst++ = readl_relaxed(priv->fuses + offset); in apple_efuses_read()
53 priv->fuses = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in apple_efuses_probe()
54 if (IS_ERR(priv->fuses)) in apple_efuses_probe()
55 return PTR_ERR(priv->fuses); in apple_efuses_probe()
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| H A D | Kconfig | 278 Enable support for reading the fuses in the E-FUSE or OTP
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| /linux/drivers/crypto/intel/qat/qat_c3xxx/ |
| H A D | adf_c3xxx_hw_data.c | 28 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
32 accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET; in get_accel_mask()
40 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
52 return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK; in get_ae_mask()
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| H A D | adf_drv.c | 111 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
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| /linux/drivers/crypto/intel/qat/qat_c62x/ |
| H A D | adf_c62x_hw_data.c | 28 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
32 accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET; in get_accel_mask()
40 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
52 return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK; in get_ae_mask()
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| H A D | adf_drv.c | 111 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
154 i = (hw_data->fuses[ADF_FUSECTL0] & ADF_DEVICE_FUSECTL_MASK) ? 1 : 0; in adf_probe()
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| /linux/drivers/crypto/intel/qat/qat_dh895xcc/ |
| H A D | adf_dh895xcc_hw_data.c | 30 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_accel_mask() local
32 return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & in get_accel_mask()
38 u32 fuses = self->fuses[ADF_FUSECTL0]; in get_ae_mask() local
40 return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK; in get_ae_mask()
100 int sku = (self->fuses[ADF_FUSECTL0] & ADF_DH895XCC_FUSECTL_SKU_MASK) in get_sku()
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| H A D | adf_drv.c | 111 &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
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| /linux/drivers/pmdomain/qcom/ |
| H A D | cpr.c | 804 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_populate_ring_osc_idx() local
808 for (; fuse < end; fuse++, fuses++) { in cpr_populate_ring_osc_idx()
809 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->ring_osc, &data); in cpr_populate_ring_osc_idx()
846 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_fuse_corner_init() local
867 for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) { in cpr_fuse_corner_init()
877 uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage, in cpr_fuse_corner_init()
897 ret = nvmem_cell_read_variable_le_u32(drv->dev, fuses->quotient, &fuse->quot); in cpr_fuse_corner_init()
1068 const struct cpr_fuse *fuses = drv->cpr_fuses; in cpr_corner_init() local
1166 quot_offset = fuses[fnum].quotient_offset; in cpr_corner_init()
1219 struct cpr_fuse *fuses; in cpr_get_fuses() local
[all...] |
| /linux/drivers/crypto/intel/qat/qat_6xxx/ |
| H A D | adf_drv.c | 90 pci_read_config_dword(pdev, ADF_GEN6_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]); in adf_probe()
91 pci_read_config_dword(pdev, ADF_GEN6_FUSECTL0_OFFSET, &hw_data->fuses[ADF_FUSECTL0]); in adf_probe()
92 pci_read_config_dword(pdev, ADF_GEN6_FUSECTL1_OFFSET, &hw_data->fuses[ADF_FUSECTL1]); in adf_probe()
94 if (!(hw_data->fuses[ADF_FUSECTL1] & ICP_ACCEL_GEN6_MASK_WCP_WAT_SLICE)) in adf_probe()
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| H A D | adf_6xxx_hw_data.c | 636 unsigned long fuses = self->fuses[ADF_FUSECTL4]; in get_ae_mask() local
640 * If bit 0 is set in the fuses, the first 4 engines are disabled. in get_ae_mask()
644 if (test_bit(0, &fuses)) in get_ae_mask()
647 if (test_bit(4, &fuses)) in get_ae_mask()
650 if (test_bit(8, &fuses)) in get_ae_mask()
664 fusectl1 = GET_HW_DATA(accel_dev)->fuses[ADF_FUSECTL1]; in get_accel_cap()
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| /linux/drivers/crypto/intel/qat/qat_common/ |
| H A D | adf_gen2_hw_data.c | 120 u32 fuses = hw_data->fuses[ADF_FUSECTL0]; in adf_gen2_get_accel_cap() local
146 if ((straps | fuses) & ADF_POWERGATE_PKE) in adf_gen2_get_accel_cap()
149 if ((straps | fuses) & ADF_POWERGATE_DC) in adf_gen2_get_accel_cap()
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| H A D | adf_accel_devices.h | 334 u32 fuses[ADF_MAX_FUSES]; member
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| /linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | imx-cpufreq-dt.txt | 5 "speed grading" value which are written in fuses. These bits are combined with
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| /linux/drivers/crypto/intel/qat/qat_420xx/ |
| H A D | adf_drv.c | 82 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]); in adf_probe()
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| H A D | adf_420xx_hw_data.c | 99 u32 me_disable = self->fuses[ADF_FUSECTL4]; in get_ae_mask()
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| /linux/drivers/crypto/intel/qat/qat_4xxx/ |
| H A D | adf_drv.c | 84 pci_read_config_dword(pdev, ADF_GEN4_FUSECTL4_OFFSET, &hw_data->fuses[ADF_FUSECTL4]); in adf_probe()
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| H A D | adf_4xxx_hw_data.c | 103 u32 me_disable = self->fuses[ADF_FUSECTL4]; in get_ae_mask()
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-asus-tf201.dts | 590 /delete-property/ nvidia,xcvr-setup-use-fuses;
595 /delete-property/ nvidia,xcvr-setup-use-fuses;
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| H A D | tegra30.dtsi | 1143 nvidia,xcvr-setup-use-fuses;
1186 nvidia,xcvr-setup-use-fuses;
1228 nvidia,xcvr-setup-use-fuses;
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| /linux/drivers/nvme/target/ |
| H A D | passthru.c | 138 id->fuses = 0; in nvmet_passthru_override_id_ctrl()
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| /linux/Documentation/security/keys/ |
| H A D | trusted-encrypted.rst | 36 fuses and is accessible to TEE only.
48 in the on-chip fuses and is accessible to the DCP encryption engine only.
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| /linux/include/linux/ |
| H A D | nvme.h | 371 __le16 fuses; member
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mn.dtsi | 581 * reg = <0x4 0x8> describes fuses 0x410 and
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