Searched refs:ecc_ctrl (Results 1 – 4 of 4) sorted by relevance
205 u32 ecc_ctrl; member 312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG); in rnandc_select_target() 1042 rnand->ecc_ctrl |= ECC_CTRL_CAP_2B; in rnandc_hw_ecc_controller_init() 1046 rnand->ecc_ctrl |= ECC_CTRL_CAP_4B; in rnandc_hw_ecc_controller_init() 1050 rnand->ecc_ctrl |= ECC_CTRL_CAP_8B; in rnandc_hw_ecc_controller_init() 1054 rnand->ecc_ctrl |= ECC_CTRL_CAP_16B; in rnandc_hw_ecc_controller_init() 1058 rnand->ecc_ctrl |= ECC_CTRL_CAP_24B; in rnandc_hw_ecc_controller_init() 1062 rnand->ecc_ctrl |= ECC_CTRL_CAP_32B; in rnandc_hw_ecc_controller_init() 1069 rnand->ecc_ctrl |= ECC_CTRL_ERR_THRESHOLD(chip->ecc.strength); in rnandc_hw_ecc_controller_init()
307 u32 ecc_ctrl; /* DRAM ECC Control reg */ member
416 static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS]; variable 472 if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) || in dnv_get_registers() 1080 if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) { in check_unit()
1366 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in umc_dump_misc_regs() 2939 umc->ecc_ctrl = tmp; in umc_read_mc_regs() 3559 edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl); in gpu_dump_misc_regs() 3670 umc->ecc_ctrl = tmp; in gpu_read_mc_regs()