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Searched refs:div_table (Results 1 – 25 of 27) sorted by relevance

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/linux/drivers/clk/ti/
H A Ddivider.c331 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, in ti_clk_parse_divider_data() argument
339 if (!div_table) { in ti_clk_parse_divider_data()
349 if (div_table[i] == -1) in ti_clk_parse_divider_data()
351 if (div_table[i]) in ti_clk_parse_divider_data()
365 if (div_table[i] > 0) { in ti_clk_parse_divider_data()
366 tmp[valid_div].div = div_table[i]; in ti_clk_parse_divider_data()
369 if (div_table[i] > max_div) in ti_clk_parse_divider_data()
370 max_div = div_table[i]; in ti_clk_parse_divider_data()
371 if (!min_div || div_table[i] < min_div) in ti_clk_parse_divider_data()
372 min_div = div_table[ in ti_clk_parse_divider_data()
[all...]
H A Dclock.h214 int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
/linux/drivers/clk/mediatek/
H A Dclk-pll.c142 const struct mtk_pll_div_table *div_table = pll->data->div_table; in mtk_pll_calc_values() local
150 if (div_table) { in mtk_pll_calc_values()
151 if (freq > div_table[0].freq) in mtk_pll_calc_values()
152 freq = div_table[0].freq; in mtk_pll_calc_values()
154 for (val = 0; div_table[val + 1].freq != 0; val++) { in mtk_pll_calc_values()
155 if (freq > div_table[val + 1].freq) in mtk_pll_calc_values()
H A Dclk-mt7986-apmixed.c32 .pcw_shift = _pcw_shift, .div_table = _div_table, \
H A Dclk-mt7981-apmixed.c34 .pcw_shift = _pcw_shift, .div_table = _div_table, \
H A Dclk-pll.h47 const struct mtk_pll_div_table *div_table; member
H A Dclk-mt8516-apmixedsys.c40 .div_table = _div_table, \
H A Dclk-mt8167-apmixedsys.c39 .div_table = _div_table, \
H A Dclk-mt2712-apmixedsys.c41 .div_table = _div_table, \
H A Dclk-mt8183-apmixedsys.c78 .div_table = _div_table, \
H A Dclk-mt8173-apmixedsys.c41 .div_table = _div_table, \
H A Dclk-mt7629.c40 .div_table = _div_table, \
H A Dclk-mt6797.c616 .div_table = _div_table, \
H A Dclk-mt6779.c1169 .div_table = _div_table, \
/linux/drivers/clk/mmp/
H A Dclk-mix.c34 if (mix->div_table) { in _get_maxdiv()
35 for (clkt = mix->div_table; clkt->div; clkt++) in _get_maxdiv()
51 if (mix->div_table) { in _get_div()
52 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div()
88 if (mix->div_table) { in _get_div_val()
89 for (clkt = mix->div_table; clkt->div; clkt++) in _get_div_val()
H A Dclk.h77 struct clk_div_table *div_table; member
87 struct clk_div_table *div_table; member
/linux/drivers/clk/ingenic/
H A Dcgu.c423 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
424 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
444 && clk_info->div.div_table[i]; i++) { in ingenic_clk_calc_hw_div()
445 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
446 clk_info->div.div_table[i] < best) { in ingenic_clk_calc_hw_div()
447 best = clk_info->div.div_table[i]; in ingenic_clk_calc_hw_div()
473 if (clk_info->div.div_table) { in ingenic_clk_calc_div()
476 return clk_info->div.div_table[hw_div]; in ingenic_clk_calc_div()
542 if (clk_info->div.div_table) in ingenic_clk_set_rate()
H A Dcgu.h97 * @div_table: optional table to map the value read from the register to the
109 const u8 *div_table; member
/linux/drivers/clk/
H A Dclk-aspeed.h72 * @div_table: Common divider lookup table
78 const struct clk_div_table *div_table; member
H A Dclk-stm32f4.c561 const struct clk_div_table *div_table; member
599 const struct clk_div_table *div_table; member
976 div_data[i].div_table, in stm32f4_rcc_register_pll()
1913 post_div->div_table, in stm32f4_rcc_init()
/linux/arch/m68k/atari/
H A Ddebug.c214 static int div_table[9] = in atari_init_scc_port() local
229 div = div_table[baud]; in atari_init_scc_port()
/linux/drivers/clk/x86/
H A Dclk-cgu.h188 const struct clk_div_table *div_table; member
238 .div_table = _dtable, \
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c393 const u8 *div_table; in g33_get_cdclk() local
408 div_table = div_3200; in g33_get_cdclk()
411 div_table = div_4000; in g33_get_cdclk()
414 div_table = div_4800; in g33_get_cdclk()
417 div_table = div_5333; in g33_get_cdclk()
424 div_table[cdclk_sel]); in g33_get_cdclk()
475 const u8 *div_table; in i965gm_get_cdclk() local
490 div_table = div_3200; in i965gm_get_cdclk()
493 div_table = div_4000; in i965gm_get_cdclk()
496 div_table in i965gm_get_cdclk()
[all...]
/linux/drivers/clk/rockchip/
H A Dclk.h697 struct clk_div_table *div_table; member
780 .div_table = dt, \
839 .div_table = dt, \
986 .div_table = dt, \
/linux/drivers/clk/qcom/
H A Dgcc-ipq4019.c66 * @div_table: mapping for actual divider value to register divider value
75 const struct clk_div_table *div_table; member
274 for (clkt = pll->div_table; clkt->div; clkt++) { in clk_regmap_clk_div_recalc_rate()
393 .div_table = fepllwcss_clk_div_table,
412 .div_table = fepllwcss_clk_div_table,

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