| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_mdp_rdma.c | 96 struct cmdq_client_reg cmdq_reg; member
155 FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV, &priv->cmdq_reg, in mtk_mdp_rdma_fifo_config()
165 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start()
173 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop()
175 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
176 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
190 mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
192 mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt), &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
196 mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg, in mtk_mdp_rdma_config()
199 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, pri in mtk_mdp_rdma_config()
[all...] |
| H A D | mtk_ddp_comp.c | 66 struct cmdq_client_reg cmdq_reg; member
70 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write() argument
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
76 cmdq_reg->offset + offset, value); in mtk_ddp_write()
83 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_relaxed() argument
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
89 cmdq_reg->offset + offset, value); in mtk_ddp_write_relaxed()
96 struct cmdq_client_reg *cmdq_reg, void __iomem *regs, in mtk_ddp_write_mask() argument
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask()
102 cmdq_reg in mtk_ddp_write_mask()
128 mtk_dither_set_common(void __iomem * regs,struct cmdq_client_reg * cmdq_reg,unsigned int bpc,unsigned int cfg,unsigned int dither_en,struct cmdq_pkt * cmdq_pkt) mtk_dither_set_common() argument
[all...] |
| H A D | mtk_disp_ccorr.c | 39 struct cmdq_client_reg cmdq_reg; member
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
125 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); in mtk_ccorr_ctm_set()
127 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1); in mtk_ccorr_ctm_set()
129 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2); in mtk_ccorr_ctm_set()
131 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); in mtk_ccorr_ctm_set()
133 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); in mtk_ccorr_ctm_set()
173 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_disp_ccorr_probe()
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| H A D | mtk_disp_rdma.c | 84 struct cmdq_client_reg cmdq_reg; member
193 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
195 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
213 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); in mtk_rdma_config()
270 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); in mtk_rdma_layer_config()
273 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
277 &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0, in mtk_rdma_layer_config()
280 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
284 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
286 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdm in mtk_rdma_layer_config()
[all...] |
| H A D | mtk_disp_ovl.c | 164 struct cmdq_client_reg cmdq_reg; member
292 &ovl->cmdq_reg, ovl->regs, in mtk_ovl_set_afbc()
309 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CLRFMT_EXT, in mtk_ovl_set_bit_depth()
320 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_config()
327 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, in mtk_ovl_config()
330 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
331 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
376 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
388 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx)); in mtk_ovl_layer_on()
389 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ov in mtk_ovl_layer_on()
[all...] |
| H A D | mtk_disp_color.c | 42 struct cmdq_client_reg cmdq_reg; member
66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config()
67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config()
115 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_disp_color_probe()
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| H A D | mtk_padding.c | 30 * @cmdq_reg: CMDQ setting of the Padding
38 struct cmdq_client_reg cmdq_reg; member
116 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); in mtk_padding_probe()
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| H A D | mtk_ddp_comp.h | 357 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
360 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
363 struct cmdq_client_reg *cmdq_reg, void __iomem *regs,
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