Home
last modified time | relevance | path

Searched refs:clk_zero (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy.c47 timing->clk_zero = clk_z + 8 - temp; in dsi_dphy_timing_calc_clk_zero()
80 /* Calculate clk_zero after clk_prepare and hs_rqst */ in msm_dsi_dphy_timing_calc()
118 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui; in msm_dsi_dphy_timing_calc()
137 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc()
190 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v2()
230 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui; in msm_dsi_dphy_timing_calc_v2()
251 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v2()
298 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false); in msm_dsi_dphy_timing_calc_v3()
338 temp += (((timing->clk_zero + 3) << 3) + 11) * ui; in msm_dsi_dphy_timing_calc_v3()
361 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero, in msm_dsi_dphy_timing_calc_v3()
[all...]
H A Ddsi_phy_20nm.c15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
H A Ddsi_phy.h69 u32 clk_zero; member
H A Ddsi_phy_10nm.c846 writel(timing->clk_zero, base + REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1); in dsi_10nm_phy_enable()
H A Ddsi_phy_7nm.c1109 writel(timing->clk_zero, base + REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1); in dsi_7nm_phy_enable()
/linux/drivers/phy/
H A Dphy-core-mipi-dphy.c46 cfg->clk_zero = 262000; in phy_mipi_dphy_calc_config()
138 if ((cfg->clk_prepare + cfg->clk_zero) < 300000) in phy_mipi_dphy_config_validate()
/linux/include/linux/phy/
H A Dphy-mipi-dphy.h95 * @clk_zero:
100 unsigned int clk_zero; member
/linux/drivers/phy/amlogic/
H A Dphy-meson-axg-mipi-dphy.c251 (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) | in phy_meson_axg_mipi_dphy_power_on()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c320 u8 clk_zero; member
1251 val = T_CLK_ZERO(timing->clk_zero) | T_CLK_PREPARE(timing->clk_prepare); in samsung_mipi_dphy_clk_lane_timing_init()
/linux/drivers/gpu/drm/bridge/
H A Dnwl-dsi.c235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); in nwl_dsi_config_host()
/linux/drivers/media/i2c/
H A Dtc358746.c616 val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1; in tc358746_apply_dphy_config()