| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 109 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base) in dcn3_init_clocks() argument
111 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn3_init_clocks()
114 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn3_init_clocks()
115 clk_mgr_base->clks.p_state_change_support = true; in dcn3_init_clocks()
116 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn3_init_clocks()
119 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
122 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn3_init_clocks()
134 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
140 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
145 &clk_mgr_base in dcn3_init_clocks()
193 dcn3_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower) dcn3_update_clocks() argument
324 dcn3_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn3_notify_wm_ranges() argument
356 dcn3_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode) dcn3_set_hard_min_memclk() argument
377 dcn3_set_hard_max_memclk(struct clk_mgr * clk_mgr_base) dcn3_set_hard_max_memclk() argument
388 dcn3_set_max_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz) dcn3_set_max_memclk() argument
397 dcn3_set_min_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz) dcn3_set_min_memclk() argument
407 dcn3_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base) dcn3_get_memclk_states_from_smu() argument
430 dcn3_is_smu_present(struct clk_mgr * clk_mgr_base) dcn3_is_smu_present() argument
455 dcn3_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn3_enable_pme_wa() argument
466 dcn30_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link) dcn30_notify_link_rate_change() argument
[all...] |
| H A D | dcn30m_clk_mgr.c | 31 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set) in dcn30m_set_smartmux_switch() argument
33 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn30m_set_smartmux_switch()
|
| H A D | dcn30m_clk_mgr.h | 29 uint32_t dcn30m_set_smartmux_switch(struct clk_mgr *clk_mgr_base, uint32_t pins_to_set);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 216 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base) in dcn401_init_clocks() argument
218 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn401_init_clocks()
222 if (!clk_mgr_base->bw_params) in dcn401_init_clocks()
225 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn401_init_clocks()
227 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn401_init_clocks()
228 clk_mgr_base->clks.p_state_change_support = true; in dcn401_init_clocks()
229 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn401_init_clocks()
230 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn401_init_clocks()
234 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn401_init_clocks()
245 &clk_mgr_base in dcn401_init_clocks()
314 dcn401_is_dc_mode_present(struct clk_mgr * clk_mgr_base) dcn401_is_dc_mode_present() argument
334 dcn401_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) dcn401_dump_clk_registers() argument
643 dcn401_execute_block_sequence(struct clk_mgr * clk_mgr_base,unsigned int num_steps) dcn401_execute_block_sequence() argument
765 dcn401_build_update_bandwidth_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower) dcn401_build_update_bandwidth_clocks_sequence() argument
1078 dcn401_build_update_display_clocks_sequence(struct clk_mgr * clk_mgr_base,struct dc_state * context,struct dc_clocks * new_clocks,bool safe_to_lower) dcn401_build_update_display_clocks_sequence() argument
1218 dcn401_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower) dcn401_update_clocks() argument
1301 dcn401_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn401_notify_wm_ranges() argument
1327 dcn401_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode) dcn401_set_hard_min_memclk() argument
1360 dcn401_get_hard_min_memclk(struct clk_mgr * clk_mgr_base) dcn401_get_hard_min_memclk() argument
1367 dcn401_get_hard_min_fclk(struct clk_mgr * clk_mgr_base) dcn401_get_hard_min_fclk() argument
1375 dcn401_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base) dcn401_get_memclk_states_from_smu() argument
1453 dcn401_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn401_enable_pme_wa() argument
1463 dcn401_is_smu_present(struct clk_mgr * clk_mgr_base) dcn401_is_smu_present() argument
1470 dcn401_get_dtb_ref_freq_khz(struct clk_mgr * clk_mgr_base) dcn401_get_dtb_ref_freq_khz() argument
1487 dcn401_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base) dcn401_get_dispclk_from_dentist() argument
1503 dcn401_get_max_clock_khz(struct clk_mgr * clk_mgr_base,enum clk_type clk_type) dcn401_get_max_clock_khz() argument
[all...] |
| H A D | dcn401_clk_mgr.h | 107 void dcn401_init_clocks(struct clk_mgr *clk_mgr_base);
108 bool dcn401_is_dc_mode_present(struct clk_mgr *clk_mgr_base);
115 unsigned int dcn401_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 162 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base) in dcn32_init_clocks() argument
164 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn32_init_clocks()
169 if (!clk_mgr_base->bw_params) in dcn32_init_clocks()
172 num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entries_per_clk; in dcn32_init_clocks()
174 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks)); in dcn32_init_clocks()
175 clk_mgr_base->clks.p_state_change_support = true; in dcn32_init_clocks()
176 clk_mgr_base->clks.prev_p_state_change_support = true; in dcn32_init_clocks()
177 clk_mgr_base->clks.fclk_prev_p_state_change_support = true; in dcn32_init_clocks()
181 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver)) in dcn32_init_clocks()
192 &clk_mgr_base in dcn32_init_clocks()
474 dcn32_get_dispclk_from_dentist(struct clk_mgr * clk_mgr_base) dcn32_get_dispclk_from_dentist() argument
621 dcn32_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower) dcn32_update_clocks() argument
873 dcn32_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) dcn32_dump_clk_registers() argument
968 dcn32_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn32_notify_wm_ranges() argument
994 dcn32_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode) dcn32_set_hard_min_memclk() argument
1015 dcn32_set_hard_max_memclk(struct clk_mgr * clk_mgr_base) dcn32_set_hard_max_memclk() argument
1026 dcn32_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base) dcn32_get_memclk_states_from_smu() argument
1093 dcn32_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn32_enable_pme_wa() argument
1103 dcn32_is_smu_present(struct clk_mgr * clk_mgr_base) dcn32_is_smu_present() argument
1109 dcn32_set_max_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz) dcn32_set_max_memclk() argument
1119 dcn32_set_min_memclk(struct clk_mgr * clk_mgr_base,unsigned int memclk_mhz) dcn32_set_min_memclk() argument
[all...] |
| H A D | dcn32_clk_mgr.h | 28 void dcn32_init_clocks(struct clk_mgr *clk_mgr_base);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 86 static void rn_set_low_power_state(struct clk_mgr *clk_mgr_base) in rn_set_low_power_state() argument
89 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_set_low_power_state()
90 struct dc *dc = clk_mgr_base->ctx->dc; in rn_set_low_power_state()
93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()
101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()
131 static void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks() argument
135 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rn_update_clocks()
137 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks()
143 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in rn_update_clocks()
154 if (clk_mgr_base in rn_update_clocks()
284 rn_dump_clk_registers_internal(struct rn_clk_internal * internal,struct clk_mgr * clk_mgr_base) rn_dump_clk_registers_internal() argument
306 rn_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) rn_dump_clk_registers() argument
438 rn_enable_pme_wa(struct clk_mgr * clk_mgr_base) rn_enable_pme_wa() argument
512 rn_notify_wm_ranges(struct clk_mgr * clk_mgr_base) rn_notify_wm_ranges() argument
545 rn_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link) rn_notify_link_rate_change() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 119 * , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) || in ramp_up_dispclk_with_dpp()
120 * new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) in ramp_up_dispclk_with_dpp()
141 * for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we in ramp_up_dispclk_with_dpp()
143 * for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz, in ramp_up_dispclk_with_dpp()
145 * new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz, in ramp_up_dispclk_with_dpp()
187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_update_clocks()
192 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
225 || new_clocks->phyclk_khz > clk_mgr_base in rv1_update_clocks()
291 rv1_enable_pme_wa(struct clk_mgr * clk_mgr_base) rv1_enable_pme_wa() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 102 static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn316_disable_otg_wa() argument
105 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_disable_otg_wa()
128 static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base) in dcn316_enable_pme_wa() argument
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_enable_pme_wa()
135 static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base, in dcn316_update_clocks() argument
140 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn316_update_clocks()
142 struct dc *dc = clk_mgr_base->ctx->dc; in dcn316_update_clocks()
155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn316_update_clocks()
157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn316_update_clocks()
159 clk_mgr_base in dcn316_update_clocks()
256 dcn316_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) dcn316_dump_clk_registers() argument
403 dcn316_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn316_notify_wm_ranges() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
191 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
195 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
203 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce112_update_clocks()
207 if (dm_pp_apply_power_level_change_request(clk_mgr_base in dce112_update_clocks()
[all...] |
| H A D | dce112_clk_mgr.h | 35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| H A D | dce60_clk_mgr.c | 83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz() argument
85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz()
120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() argument
124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks()
132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce60_update_clocks()
136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
144 dce60_pplib_apply_display_requirements(clk_mgr_base in dce60_update_clocks()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.c | 129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz() argument
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz()
155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz() argument
157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz()
159 return dce_adjust_dp_ref_freq_for_ss(clk_mgr_dce, clk_mgr_base->dprefclk_khz); in dce12_get_dp_ref_freq_khz()
195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() argument
198 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_required_clocks_state()
230 struct clk_mgr *clk_mgr_base, in dce_set_clock() argument
233 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_set_clock()
235 struct dc_bios *bp = clk_mgr_base in dce_set_clock()
402 dce_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower) dce_update_clocks() argument
[all...] |
| H A D | dce_clk_mgr.h | 34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 100 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable) in dcn315_disable_otg_wa() argument
102 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_disable_otg_wa()
125 static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base, in dcn315_update_clocks() argument
130 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn315_update_clocks()
132 struct dc *dc = clk_mgr_base->ctx->dc; in dcn315_update_clocks()
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn315_update_clocks()
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
153 if (clk_mgr_base in dcn315_update_clocks()
249 dcn315_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) dcn315_dump_clk_registers() argument
438 dcn315_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn315_notify_wm_ranges() argument
586 dcn315_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn315_enable_pme_wa() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 148 static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn314_disable_otg_wa() argument
151 struct dc *dc = clk_mgr_base->ctx->dc; in dcn314_disable_otg_wa()
174 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base) in dcn314_is_spll_ssc_enabled() argument
176 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_is_spll_ssc_enabled()
205 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base, in dcn314_update_clocks() argument
210 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn314_update_clocks()
212 struct dc *dc = clk_mgr_base->ctx->dc; in dcn314_update_clocks()
227 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn314_update_clocks()
229 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true); in dcn314_update_clocks()
230 clk_mgr_base in dcn314_update_clocks()
362 dcn314_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn314_enable_pme_wa() argument
389 dcn314_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) dcn314_dump_clk_registers() argument
541 dcn314_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn314_notify_wm_ranges() argument
[all...] |
| H A D | dcn314_clk_mgr.h | 53 bool dcn314_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base);
57 void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
|
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.c | 189 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_disable_otg_wa() argument
192 struct dc *dc = clk_mgr_base->ctx->dc; in dcn35_disable_otg_wa()
201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_disable_otg_wa()
341 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context, in dcn35_notify_host_router_bw() argument
345 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_notify_host_router_bw()
370 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) { in dcn35_notify_host_router_bw()
371 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i]; in dcn35_notify_host_router_bw()
377 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, in dcn35_update_clocks() argument
382 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dcn35_update_clocks()
384 struct dc *dc = clk_mgr_base in dcn35_update_clocks()
563 dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base) dcn35_enable_pme_wa() argument
595 dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base) dcn35_is_spll_ssc_enabled() argument
802 dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base) dcn35_notify_wm_ranges() argument
1073 dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base) dcn35_set_low_power_state() argument
1087 dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base) dcn35_exit_low_power_state() argument
1096 dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base) dcn35_is_ips_supported() argument
[all...] |
| H A D | dcn35_clk_mgr.h | 52 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 95 static void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks() argument
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in vg_update_clocks()
101 struct dc *dc = clk_mgr_base->ctx->dc; in vg_update_clocks()
116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in vg_update_clocks()
128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()
133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in vg_update_clocks()
138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()
142 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) { in vg_update_clocks()
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base in vg_update_clocks()
216 vg_dump_clk_registers_internal(struct dcn301_clk_internal * internal,struct clk_mgr * clk_mgr_base) vg_dump_clk_registers_internal() argument
238 vg_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr * clk_mgr_base,struct clk_log_info * log_info) vg_dump_clk_registers() argument
370 vg_enable_pme_wa(struct clk_mgr * clk_mgr_base) vg_enable_pme_wa() argument
442 vg_notify_wm_ranges(struct clk_mgr * clk_mgr_base) vg_notify_wm_ranges() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.c | 249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks() argument
253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks()
261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce11_update_clocks()
265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce11_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 45 void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
54 int dcn31_get_dtb_ref_freq_khz(struct clk_mgr *clk_mgr_base);
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 299 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info);
336 int (*get_dispclk_from_dentist)(struct clk_mgr *clk_mgr_base);
342 unsigned int (*get_max_clock_khz)(struct clk_mgr *clk_mgr_base, enum clk_type clk_type);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.h | 56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
|