| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_mode_vba_314.h | 40 long WritebackDestinationWidth,
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| H A D | display_mode_vba_314.c | 276 int WritebackDestinationWidth,
2052 v->WritebackDestinationWidth[k],
2529 v->WritebackDestinationWidth[k],
2545 v->WritebackDestinationWidth[j],
3208 WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
3211 WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
3470 long WritebackDestinationWidth, argument
3477 DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
3478 DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
3487 int WritebackDestinationWidth, argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.h | 39 long WritebackDestinationWidth,
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| H A D | display_mode_vba_31.c | 267 int WritebackDestinationWidth,
2034 v->WritebackDestinationWidth[k],
2510 v->WritebackDestinationWidth[k],
2526 v->WritebackDestinationWidth[j],
3189 WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
3192 WRBandwidth = v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k]
3364 long WritebackDestinationWidth, argument
3371 DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal;
3372 DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth;
3381 int WritebackDestinationWidth, argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_mode_vba_30.h | 39 long WritebackDestinationWidth,
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| H A D | display_mode_vba_30.c | 274 long WritebackDestinationWidth,
342 double WritebackDestinationWidth[],
1883 v->WritebackDestinationWidth[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2356 v->WritebackDestinationWidth[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2371 v->WritebackDestinationWidth[j], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2778 v->WritebackDestinationWidth, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3229 long WritebackDestinationWidth, in dml30_CalculateWriteBackDISPCLK() argument
3236 DISPCLK_V = PixelClock * (WritebackVTaps * dml_ceil(WritebackDestinationWidth / 6.0, 1) + 8.0) / HTotal; in dml30_CalculateWriteBackDISPCLK()
3237 DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / WritebackSourceWidth; in dml30_CalculateWriteBackDISPCLK()
3246 long WritebackDestinationWidth, in CalculateWriteBackDelay() argument
5179 CalculateWatermarksAndDRAMSpeedChangeSupport(struct display_mode_lib * mode_lib,unsigned int PrefetchMode,unsigned int NumberOfActivePlanes,unsigned int MaxLineBufferLines,unsigned int LineBufferSize,unsigned int DPPOutputBufferPixels,unsigned int DETBufferSizeInKByte,unsigned int WritebackInterfaceBufferSize,double DCFCLK,double ReturnBW,bool GPUVMEnable,unsigned int dpte_group_bytes[],unsigned int MetaChunkSize,double UrgentLatency,double ExtraLatency,double WritebackLatency,double WritebackChunkSize,double SOCCLK,double DRAMClockChangeLatency,double SRExitTime,double SREnterPlusExitTime,double DCFCLKDeepSleep,unsigned int DPPPerPlane[],bool DCCEnable[],double DPPCLK[],unsigned int DETBufferSizeY[],unsigned int DETBufferSizeC[],unsigned int SwathHeightY[],unsigned int SwathHeightC[],unsigned int LBBitPerPixel[],double SwathWidthY[],double SwathWidthC[],double HRatio[],double HRatioChroma[],unsigned int vtaps[],unsigned int VTAPsChroma[],double VRatio[],double VRatioChroma[],unsigned int HTotal[],double PixelClock[],unsigned int BlendingAndTiming[],double BytePerPixelDETY[],double BytePerPixelDETC[],double DSTXAfterScaler[],double DSTYAfterScaler[],bool WritebackEnable[],enum source_format_class WritebackPixelFormat[],double WritebackDestinationWidth[],double WritebackDestinationHeight[],double WritebackSourceHeight[],enum clock_change_support * DRAMClockChangeSupport,double * UrgentWatermark,double * WritebackUrgentWatermark,double * DRAMClockChangeWatermark,double * WritebackDRAMClockChangeWatermark,double * StutterExitWatermark,double * StutterEnterPlusExitWatermark,double * MinActiveDRAMClockChangeLatencySupported) CalculateWatermarksAndDRAMSpeedChangeSupport() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 665 mode_lib->vba.WritebackDestinationWidth[mode_lib->vba.NumberOfActivePlanes] = in fetch_pipe_params()
1126 double WritebackDestinationWidth, in CalculateWriteBackDISPCLK() argument
1132 dml_max((WritebackLumaVTaps * dml_ceil(1.0 / WritebackVRatio, 1) * dml_ceil(WritebackDestinationWidth / 4.0, 1) in CalculateWriteBackDISPCLK()
1133 + dml_ceil(WritebackDestinationWidth / 4.0, 1)) / (double) HTotal + dml_ceil(1.0 / WritebackVRatio, 1) in CalculateWriteBackDISPCLK()
1135 dml_ceil(1.0 / WritebackVRatio, 1) * WritebackDestinationWidth / (double) HTotal)); in CalculateWriteBackDISPCLK()
1139 dml_max((WritebackChromaVTaps * dml_ceil(1 / (2 * WritebackVRatio), 1) * dml_ceil(WritebackDestinationWidth / 2.0 / 2.0, 1) in CalculateWriteBackDISPCLK()
1140 + dml_ceil(WritebackDestinationWidth / 2.0 / WritebackChromaLineBufferWidth, 1)) / HTotal in CalculateWriteBackDISPCLK()
1142 dml_ceil(1.0 / (2 * WritebackVRatio), 1) * WritebackDestinationWidth / 2.0 / HTotal))); in CalculateWriteBackDISPCLK()
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| H A D | display_mode_vba.h | 486 double WritebackDestinationWidth[DC__NUM_DPP__MAX]; member
1257 double WritebackDestinationWidth,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_mode_vba_21.c | 284 unsigned int WritebackDestinationWidth);
331 double WritebackDestinationWidth[],
1492 mode_lib->vba.WritebackDestinationWidth[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2051 mode_lib->vba.WritebackDestinationWidth[k]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2070 mode_lib->vba.WritebackDestinationWidth[j]) in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2460 mode_lib->vba.WritebackDestinationWidth, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3070 unsigned int WritebackDestinationWidth) in CalculateWriteBackDelay() argument
3077 WritebackDestinationWidth in CalculateWriteBackDelay()
3104 WritebackDestinationWidth in CalculateWriteBackDelay()
3643 locals->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[ in dml21_ModeSupportAndSystemConfigurationFull()
5239 CalculateWatermarksAndDRAMSpeedChangeSupport(struct display_mode_lib * mode_lib,unsigned int PrefetchMode,unsigned int NumberOfActivePlanes,unsigned int MaxLineBufferLines,unsigned int LineBufferSize,unsigned int DPPOutputBufferPixels,unsigned int DETBufferSizeInKByte,unsigned int WritebackInterfaceLumaBufferSize,unsigned int WritebackInterfaceChromaBufferSize,double DCFCLK,double UrgentOutOfOrderReturn,double ReturnBW,bool GPUVMEnable,int dpte_group_bytes[],unsigned int MetaChunkSize,double UrgentLatency,double ExtraLatency,double WritebackLatency,double WritebackChunkSize,double SOCCLK,double DRAMClockChangeLatency,double SRExitTime,double SREnterPlusExitTime,double DCFCLKDeepSleep,int DPPPerPlane[],bool DCCEnable[],double DPPCLK[],double SwathWidthSingleDPPY[],unsigned int SwathHeightY[],double ReadBandwidthPlaneLuma[],unsigned int SwathHeightC[],double ReadBandwidthPlaneChroma[],unsigned int LBBitPerPixel[],double SwathWidthY[],double HRatio[],unsigned int vtaps[],unsigned int VTAPsChroma[],double VRatio[],unsigned int HTotal[],double PixelClock[],unsigned int BlendingAndTiming[],double BytePerPixelDETY[],double BytePerPixelDETC[],bool WritebackEnable[],enum source_format_class WritebackPixelFormat[],double WritebackDestinationWidth[],double WritebackDestinationHeight[],double WritebackSourceHeight[],enum clock_change_support * DRAMClockChangeSupport,double * UrgentWatermark,double * WritebackUrgentWatermark,double * DRAMClockChangeWatermark,double * WritebackDRAMClockChangeWatermark,double * StutterExitWatermark,double * StutterEnterPlusExitWatermark,double * MinActiveDRAMClockChangeLatencySupported) CalculateWatermarksAndDRAMSpeedChangeSupport() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_mode_vba_20.c | 228 unsigned int WritebackDestinationWidth);
1108 mode_lib->vba.WritebackDestinationWidth[k], in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1989 mode_lib->vba.WritebackDestinationWidth[k]) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2008 mode_lib->vba.WritebackDestinationWidth[j]) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2525 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2540 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2552 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2983 unsigned int WritebackDestinationWidth) in CalculateWriteBackDelay() argument
2990 WritebackDestinationWidth in CalculateWriteBackDelay()
3017 WritebackDestinationWidth in CalculateWriteBackDelay()
[all...] |
| H A D | display_mode_vba_20v2.c | 252 unsigned int WritebackDestinationWidth);
1168 mode_lib->vba.WritebackDestinationWidth[k], in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2025 mode_lib->vba.WritebackDestinationWidth[k]) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2044 mode_lib->vba.WritebackDestinationWidth[j]) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2559 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2574 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2586 / (mode_lib->vba.WritebackDestinationWidth[k] in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3056 unsigned int WritebackDestinationWidth) in CalculateWriteBackDelay() argument
3063 WritebackDestinationWidth in CalculateWriteBackDelay()
3090 WritebackDestinationWidth in CalculateWriteBackDelay()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_32.c | 95 mode_lib->vba.WritebackDestinationWidth[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
608 mode_lib->vba.WritebackDestinationWidth[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
625 mode_lib->vba.WritebackDestinationWidth[j], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1484 WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1489 WRBandwidth = mode_lib->vba.WritebackDestinationWidth[k] in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1841 v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] in dml32_ModeSupportAndSystemConfigurationFull()
1846 v->WriteBandwidth[k] = mode_lib->vba.WritebackDestinationWidth[k] in dml32_ModeSupportAndSystemConfigurationFull()
1894 if (2.0 * mode_lib->vba.WritebackDestinationWidth[k] * (mode_lib->vba.WritebackVTaps[k] - 1) in dml32_ModeSupportAndSystemConfigurationFull()
2240 mode_lib->vba.WritebackDestinationWidth[k], in dml32_ModeSupportAndSystemConfigurationFull()
2924 mode_lib->vba.WritebackDestinationWidth[ in dml32_ModeSupportAndSystemConfigurationFull()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core_structs.h | 643 dml_uint_t WritebackDestinationWidth[__DML_NUM_PLANES__]; member
1374 dml_uint_t *WritebackDestinationWidth; member
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| H A D | dml2_translation_helper.c | 1236 out->WritebackDestinationWidth[location] = wb_info->dwb_params.dest_width; in populate_dml_writeback_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 3628 unsigned int WritebackDestinationWidth, in CalculateWriteBackDelay() argument
3639 Line_length = math_max2((double)WritebackDestinationWidth, math_ceil2((double)WritebackDestinationWidth / 6.0, 1.0) * WritebackVTaps); in CalculateWriteBackDelay()
3644 CalculateWriteBackDelay = Output_lines_last_notclamped * Line_length + (HTotal - WritebackDestinationWidth) + 80; in CalculateWriteBackDelay()
4440 unsigned int WritebackDestinationWidth, in CalculateWriteBackDISPCLK() argument
4447 DISPCLK_V = PixelClock * (WritebackVTaps * math_ceil2((double)WritebackDestinationWidth / 6.0, 1) + 8.0) / (double)HTotal; in CalculateWriteBackDISPCLK()
4448 DISPCLK_HB = PixelClock * WritebackVTaps * (WritebackDestinationWidth * WritebackVTaps - WritebackLineBufferSize / 57.0) / 6.0 / (double)WritebackSourceWidth; in CalculateWriteBackDISPCLK()
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