1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/gpio/consumer.h>
10 #include <linux/i2c.h>
11 #include <linux/kernel.h>
12 #include <linux/math64.h>
13 #include <linux/media-bus-format.h>
14 #include <linux/minmax.h>
15 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <linux/units.h>
20
21 #include <drm/drm_atomic_helper.h>
22 #include <drm/drm_drv.h>
23 #include <drm/drm_mipi_dsi.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <video/mipi_display.h>
27 #include <video/videomode.h>
28
29 /* Global (16-bit addressable) */
30 #define TC358768_CHIPID 0x0000
31 #define TC358768_SYSCTL 0x0002
32 #define TC358768_CONFCTL 0x0004
33 #define TC358768_VSDLY 0x0006
34 #define TC358768_DATAFMT 0x0008
35 #define TC358768_GPIOEN 0x000E
36 #define TC358768_GPIODIR 0x0010
37 #define TC358768_GPIOIN 0x0012
38 #define TC358768_GPIOOUT 0x0014
39 #define TC358768_PLLCTL0 0x0016
40 #define TC358768_PLLCTL1 0x0018
41 #define TC358768_CMDBYTE 0x0022
42 #define TC358768_PP_MISC 0x0032
43 #define TC358768_DSITX_DT 0x0050
44 #define TC358768_FIFOSTATUS 0x00F8
45
46 /* Debug (16-bit addressable) */
47 #define TC358768_VBUFCTRL 0x00E0
48 #define TC358768_DBG_WIDTH 0x00E2
49 #define TC358768_DBG_VBLANK 0x00E4
50 #define TC358768_DBG_DATA 0x00E8
51
52 /* TX PHY (32-bit addressable) */
53 #define TC358768_CLW_DPHYCONTTX 0x0100
54 #define TC358768_D0W_DPHYCONTTX 0x0104
55 #define TC358768_D1W_DPHYCONTTX 0x0108
56 #define TC358768_D2W_DPHYCONTTX 0x010C
57 #define TC358768_D3W_DPHYCONTTX 0x0110
58 #define TC358768_CLW_CNTRL 0x0140
59 #define TC358768_D0W_CNTRL 0x0144
60 #define TC358768_D1W_CNTRL 0x0148
61 #define TC358768_D2W_CNTRL 0x014C
62 #define TC358768_D3W_CNTRL 0x0150
63
64 /* TX PPI (32-bit addressable) */
65 #define TC358768_STARTCNTRL 0x0204
66 #define TC358768_DSITXSTATUS 0x0208
67 #define TC358768_LINEINITCNT 0x0210
68 #define TC358768_LPTXTIMECNT 0x0214
69 #define TC358768_TCLK_HEADERCNT 0x0218
70 #define TC358768_TCLK_TRAILCNT 0x021C
71 #define TC358768_THS_HEADERCNT 0x0220
72 #define TC358768_TWAKEUP 0x0224
73 #define TC358768_TCLK_POSTCNT 0x0228
74 #define TC358768_THS_TRAILCNT 0x022C
75 #define TC358768_HSTXVREGCNT 0x0230
76 #define TC358768_HSTXVREGEN 0x0234
77 #define TC358768_TXOPTIONCNTRL 0x0238
78 #define TC358768_BTACNTRL1 0x023C
79
80 /* TX CTRL (32-bit addressable) */
81 #define TC358768_DSI_CONTROL 0x040C
82 #define TC358768_DSI_STATUS 0x0410
83 #define TC358768_DSI_INT 0x0414
84 #define TC358768_DSI_INT_ENA 0x0418
85 #define TC358768_DSICMD_RDFIFO 0x0430
86 #define TC358768_DSI_ACKERR 0x0434
87 #define TC358768_DSI_ACKERR_INTENA 0x0438
88 #define TC358768_DSI_ACKERR_HALT 0x043c
89 #define TC358768_DSI_RXERR 0x0440
90 #define TC358768_DSI_RXERR_INTENA 0x0444
91 #define TC358768_DSI_RXERR_HALT 0x0448
92 #define TC358768_DSI_ERR 0x044C
93 #define TC358768_DSI_ERR_INTENA 0x0450
94 #define TC358768_DSI_ERR_HALT 0x0454
95 #define TC358768_DSI_CONFW 0x0500
96 #define TC358768_DSI_LPCMD 0x0500
97 #define TC358768_DSI_RESET 0x0504
98 #define TC358768_DSI_INT_CLR 0x050C
99 #define TC358768_DSI_START 0x0518
100
101 /* DSITX CTRL (16-bit addressable) */
102 #define TC358768_DSICMD_TX 0x0600
103 #define TC358768_DSICMD_TYPE 0x0602
104 #define TC358768_DSICMD_WC 0x0604
105 #define TC358768_DSICMD_WD0 0x0610
106 #define TC358768_DSICMD_WD1 0x0612
107 #define TC358768_DSICMD_WD2 0x0614
108 #define TC358768_DSICMD_WD3 0x0616
109 #define TC358768_DSI_EVENT 0x0620
110 #define TC358768_DSI_VSW 0x0622
111 #define TC358768_DSI_VBPR 0x0624
112 #define TC358768_DSI_VACT 0x0626
113 #define TC358768_DSI_HSW 0x0628
114 #define TC358768_DSI_HBPR 0x062A
115 #define TC358768_DSI_HACT 0x062C
116
117 /* TC358768_DSI_CONTROL (0x040C) register */
118 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15)
119 #define TC358768_DSI_CONTROL_TXMD BIT(7)
120 #define TC358768_DSI_CONTROL_HSCKMD BIT(5)
121 #define TC358768_DSI_CONTROL_EOTDIS BIT(0)
122
123 /* TC358768_DSI_CONFW (0x0500) register */
124 #define TC358768_DSI_CONFW_MODE_SET (5 << 29)
125 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29)
126 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24)
127
128 /* TC358768_DSICMD_TX (0x0600) register */
129 #define TC358768_DSI_CMDTX_DC_START BIT(0)
130
131 static const char * const tc358768_supplies[] = {
132 "vddc", "vddmipi", "vddio"
133 };
134
135 struct tc358768_dsi_output {
136 struct mipi_dsi_device *dev;
137 struct drm_panel *panel;
138 struct drm_bridge *bridge;
139 };
140
141 struct tc358768_priv {
142 struct device *dev;
143 struct regmap *regmap;
144 struct gpio_desc *reset_gpio;
145 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
146 struct clk *refclk;
147 int enabled;
148 int error;
149
150 struct mipi_dsi_host dsi_host;
151 struct drm_bridge bridge;
152 struct tc358768_dsi_output output;
153
154 u32 pd_lines; /* number of Parallel Port Input Data Lines */
155 u32 dsi_lanes; /* number of DSI Lanes */
156 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
157
158 /* Parameters for PLL programming */
159 u32 fbd; /* PLL feedback divider */
160 u32 prd; /* PLL input divider */
161 u32 frs; /* PLL Freqency range for HSCK (post divider) */
162
163 u32 dsiclk; /* pll_clk / 2 */
164 u32 pclk; /* incoming pclk rate */
165 };
166
dsi_host_to_tc358768(struct mipi_dsi_host * host)167 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
168 *host)
169 {
170 return container_of(host, struct tc358768_priv, dsi_host);
171 }
172
bridge_to_tc358768(struct drm_bridge * bridge)173 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
174 *bridge)
175 {
176 return container_of(bridge, struct tc358768_priv, bridge);
177 }
178
tc358768_clear_error(struct tc358768_priv * priv)179 static int tc358768_clear_error(struct tc358768_priv *priv)
180 {
181 int ret = priv->error;
182
183 priv->error = 0;
184 return ret;
185 }
186
tc358768_write(struct tc358768_priv * priv,u32 reg,u32 val)187 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
188 {
189 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
190 int tmpval = val;
191 size_t count = 2;
192
193 if (priv->error)
194 return;
195
196 /* 16-bit register? */
197 if (reg < 0x100 || reg >= 0x600)
198 count = 1;
199
200 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
201 }
202
tc358768_read(struct tc358768_priv * priv,u32 reg,u32 * val)203 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
204 {
205 size_t count = 2;
206
207 if (priv->error)
208 return;
209
210 /* 16-bit register? */
211 if (reg < 0x100 || reg >= 0x600) {
212 *val = 0;
213 count = 1;
214 }
215
216 priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
217 }
218
tc358768_update_bits(struct tc358768_priv * priv,u32 reg,u32 mask,u32 val)219 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
220 u32 val)
221 {
222 u32 tmp, orig;
223
224 tc358768_read(priv, reg, &orig);
225
226 if (priv->error)
227 return;
228
229 tmp = orig & ~mask;
230 tmp |= val & mask;
231 if (tmp != orig)
232 tc358768_write(priv, reg, tmp);
233 }
234
tc358768_dsicmd_tx(struct tc358768_priv * priv)235 static void tc358768_dsicmd_tx(struct tc358768_priv *priv)
236 {
237 u32 val;
238
239 /* start transfer */
240 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START);
241 if (priv->error)
242 return;
243
244 /* wait transfer completion */
245 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val,
246 (val & TC358768_DSI_CMDTX_DC_START) == 0,
247 100, 100000);
248 }
249
tc358768_sw_reset(struct tc358768_priv * priv)250 static int tc358768_sw_reset(struct tc358768_priv *priv)
251 {
252 /* Assert Reset */
253 tc358768_write(priv, TC358768_SYSCTL, 1);
254 /* Release Reset, Exit Sleep */
255 tc358768_write(priv, TC358768_SYSCTL, 0);
256
257 return tc358768_clear_error(priv);
258 }
259
tc358768_hw_enable(struct tc358768_priv * priv)260 static void tc358768_hw_enable(struct tc358768_priv *priv)
261 {
262 int ret;
263
264 if (priv->enabled)
265 return;
266
267 ret = clk_prepare_enable(priv->refclk);
268 if (ret < 0)
269 dev_err(priv->dev, "error enabling refclk (%d)\n", ret);
270
271 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
272 if (ret < 0)
273 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
274
275 if (priv->reset_gpio)
276 usleep_range(200, 300);
277
278 /*
279 * The RESX is active low (GPIO_ACTIVE_LOW).
280 * DEASSERT (value = 0) the reset_gpio to enable the chip
281 */
282 gpiod_set_value_cansleep(priv->reset_gpio, 0);
283
284 /* wait for encoder clocks to stabilize */
285 usleep_range(1000, 2000);
286
287 priv->enabled = true;
288 }
289
tc358768_hw_disable(struct tc358768_priv * priv)290 static void tc358768_hw_disable(struct tc358768_priv *priv)
291 {
292 int ret;
293
294 if (!priv->enabled)
295 return;
296
297 /*
298 * The RESX is active low (GPIO_ACTIVE_LOW).
299 * ASSERT (value = 1) the reset_gpio to disable the chip
300 */
301 gpiod_set_value_cansleep(priv->reset_gpio, 1);
302
303 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
304 priv->supplies);
305 if (ret < 0)
306 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
307
308 clk_disable_unprepare(priv->refclk);
309
310 priv->enabled = false;
311 }
312
tc358768_pll_to_pclk(struct tc358768_priv * priv,u32 pll_clk)313 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
314 {
315 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
316 }
317
tc358768_pclk_to_pll(struct tc358768_priv * priv,u32 pclk)318 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
319 {
320 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
321 }
322
tc358768_calc_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode,bool verify_only)323 static int tc358768_calc_pll(struct tc358768_priv *priv,
324 const struct drm_display_mode *mode,
325 bool verify_only)
326 {
327 static const u32 frs_limits[] = {
328 1000000000,
329 500000000,
330 250000000,
331 125000000,
332 62500000
333 };
334 unsigned long refclk;
335 u32 prd, target_pll, i, max_pll, min_pll;
336 u32 frs, best_diff, best_pll, best_prd, best_fbd;
337
338 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
339
340 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */
341
342 for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
343 if (target_pll >= frs_limits[i])
344 break;
345
346 if (i == ARRAY_SIZE(frs_limits) || i == 0)
347 return -EINVAL;
348
349 frs = i - 1;
350 max_pll = frs_limits[i - 1];
351 min_pll = frs_limits[i];
352
353 refclk = clk_get_rate(priv->refclk);
354
355 best_diff = UINT_MAX;
356 best_pll = 0;
357 best_prd = 0;
358 best_fbd = 0;
359
360 for (prd = 1; prd <= 16; ++prd) {
361 u32 divisor = prd * (1 << frs);
362 u32 fbd;
363
364 for (fbd = 1; fbd <= 512; ++fbd) {
365 u32 pll, diff, pll_in;
366
367 pll = (u32)div_u64((u64)refclk * fbd, divisor);
368
369 if (pll >= max_pll || pll < min_pll)
370 continue;
371
372 pll_in = (u32)div_u64((u64)refclk, prd);
373 if (pll_in < 4000000)
374 continue;
375
376 diff = max(pll, target_pll) - min(pll, target_pll);
377
378 if (diff < best_diff) {
379 best_diff = diff;
380 best_pll = pll;
381 best_prd = prd;
382 best_fbd = fbd;
383
384 if (best_diff == 0)
385 goto found;
386 }
387 }
388 }
389
390 if (best_diff == UINT_MAX) {
391 dev_err(priv->dev, "could not find suitable PLL setup\n");
392 return -EINVAL;
393 }
394
395 found:
396 if (verify_only)
397 return 0;
398
399 priv->fbd = best_fbd;
400 priv->prd = best_prd;
401 priv->frs = frs;
402 priv->dsiclk = best_pll / 2;
403 priv->pclk = mode->clock * 1000;
404
405 return 0;
406 }
407
tc358768_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)408 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
409 struct mipi_dsi_device *dev)
410 {
411 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
412 struct drm_bridge *bridge;
413 struct drm_panel *panel;
414 struct device_node *ep;
415 int ret;
416
417 if (dev->lanes > 4) {
418 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
419 dev->lanes);
420 return -EINVAL;
421 }
422
423 /*
424 * tc358768 supports both Video and Pulse mode, but the driver only
425 * implements Video (event) mode currently
426 */
427 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
428 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
429 return -ENOTSUPP;
430 }
431
432 /*
433 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
434 * RGB888 is verified.
435 */
436 if (dev->format != MIPI_DSI_FMT_RGB888) {
437 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
438 return -ENOTSUPP;
439 }
440
441 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
442 &bridge);
443 if (ret)
444 return ret;
445
446 if (panel) {
447 bridge = drm_panel_bridge_add_typed(panel,
448 DRM_MODE_CONNECTOR_DSI);
449 if (IS_ERR(bridge))
450 return PTR_ERR(bridge);
451 }
452
453 priv->output.dev = dev;
454 priv->output.bridge = bridge;
455 priv->output.panel = panel;
456
457 priv->dsi_lanes = dev->lanes;
458 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
459
460 /* get input ep (port0/endpoint0) */
461 ret = -EINVAL;
462 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
463 if (ep) {
464 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines);
465 if (ret)
466 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
467
468 of_node_put(ep);
469 }
470
471 if (ret)
472 priv->pd_lines = priv->dsi_bpp;
473
474 drm_bridge_add(&priv->bridge);
475
476 return 0;
477 }
478
tc358768_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * dev)479 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
480 struct mipi_dsi_device *dev)
481 {
482 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
483
484 drm_bridge_remove(&priv->bridge);
485 if (priv->output.panel)
486 drm_panel_bridge_remove(priv->output.bridge);
487
488 return 0;
489 }
490
tc358768_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)491 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
492 const struct mipi_dsi_msg *msg)
493 {
494 struct tc358768_priv *priv = dsi_host_to_tc358768(host);
495 struct mipi_dsi_packet packet;
496 int ret;
497
498 if (!priv->enabled) {
499 dev_err(priv->dev, "Bridge is not enabled\n");
500 return -ENODEV;
501 }
502
503 if (msg->rx_len) {
504 dev_warn(priv->dev, "MIPI rx is not supported\n");
505 return -ENOTSUPP;
506 }
507
508 if (msg->tx_len > 8) {
509 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
510 return -ENOTSUPP;
511 }
512
513 ret = mipi_dsi_create_packet(&packet, msg);
514 if (ret)
515 return ret;
516
517 if (mipi_dsi_packet_format_is_short(msg->type)) {
518 tc358768_write(priv, TC358768_DSICMD_TYPE,
519 (0x10 << 8) | (packet.header[0] & 0x3f));
520 tc358768_write(priv, TC358768_DSICMD_WC, 0);
521 tc358768_write(priv, TC358768_DSICMD_WD0,
522 (packet.header[2] << 8) | packet.header[1]);
523 } else {
524 int i;
525
526 tc358768_write(priv, TC358768_DSICMD_TYPE,
527 (0x40 << 8) | (packet.header[0] & 0x3f));
528 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
529 for (i = 0; i < packet.payload_length; i += 2) {
530 u16 val = packet.payload[i];
531
532 if (i + 1 < packet.payload_length)
533 val |= packet.payload[i + 1] << 8;
534
535 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
536 }
537 }
538
539 tc358768_dsicmd_tx(priv);
540
541 ret = tc358768_clear_error(priv);
542 if (ret)
543 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
544 else
545 ret = packet.size;
546
547 return ret;
548 }
549
550 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
551 .attach = tc358768_dsi_host_attach,
552 .detach = tc358768_dsi_host_detach,
553 .transfer = tc358768_dsi_host_transfer,
554 };
555
tc358768_bridge_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)556 static int tc358768_bridge_attach(struct drm_bridge *bridge,
557 struct drm_encoder *encoder,
558 enum drm_bridge_attach_flags flags)
559 {
560 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
561
562 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
563 dev_err(priv->dev, "needs atomic updates support\n");
564 return -ENOTSUPP;
565 }
566
567 return drm_bridge_attach(encoder, priv->output.bridge, bridge,
568 flags);
569 }
570
571 static enum drm_mode_status
tc358768_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)572 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
573 const struct drm_display_info *info,
574 const struct drm_display_mode *mode)
575 {
576 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
577
578 if (tc358768_calc_pll(priv, mode, true))
579 return MODE_CLOCK_RANGE;
580
581 return MODE_OK;
582 }
583
tc358768_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)584 static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge,
585 struct drm_atomic_state *state)
586 {
587 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
588 int ret;
589
590 /* set FrmStop */
591 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
592
593 /* wait at least for one frame */
594 msleep(50);
595
596 /* clear PP_en */
597 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
598
599 /* set RstPtr */
600 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
601
602 ret = tc358768_clear_error(priv);
603 if (ret)
604 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
605 }
606
tc358768_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)607 static void tc358768_bridge_atomic_post_disable(struct drm_bridge *bridge,
608 struct drm_atomic_state *state)
609 {
610 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
611
612 tc358768_hw_disable(priv);
613 }
614
tc358768_setup_pll(struct tc358768_priv * priv,const struct drm_display_mode * mode)615 static int tc358768_setup_pll(struct tc358768_priv *priv,
616 const struct drm_display_mode *mode)
617 {
618 u32 fbd, prd, frs;
619 int ret;
620
621 ret = tc358768_calc_pll(priv, mode, false);
622 if (ret) {
623 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
624 return ret;
625 }
626
627 fbd = priv->fbd;
628 prd = priv->prd;
629 frs = priv->frs;
630
631 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
632 clk_get_rate(priv->refclk), fbd, prd, frs);
633 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n",
634 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
635 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
636 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
637 mode->clock * 1000);
638
639 /* PRD[15:12] FBD[8:0] */
640 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1));
641
642 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
643 tc358768_write(priv, TC358768_PLLCTL1,
644 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
645
646 /* wait for lock */
647 usleep_range(1000, 2000);
648
649 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
650 tc358768_write(priv, TC358768_PLLCTL1,
651 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
652
653 return tc358768_clear_error(priv);
654 }
655
tc358768_ns_to_cnt(u32 ns,u32 period_ps)656 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps)
657 {
658 return DIV_ROUND_UP(ns * 1000, period_ps);
659 }
660
tc358768_ps_to_ns(u32 ps)661 static u32 tc358768_ps_to_ns(u32 ps)
662 {
663 return ps / 1000;
664 }
665
tc358768_dpi_to_ns(u32 val,u32 pclk)666 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk)
667 {
668 return (u32)div_u64((u64)val * NANO, pclk);
669 }
670
671 /* Convert value in DPI pixel clock units to DSI byte count */
tc358768_dpi_to_dsi_bytes(struct tc358768_priv * priv,u32 val)672 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val)
673 {
674 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;
675 u64 n = priv->pclk;
676
677 return (u32)div_u64(m + n - 1, n);
678 }
679
tc358768_dsi_bytes_to_ns(struct tc358768_priv * priv,u32 val)680 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val)
681 {
682 u64 m = (u64)val * NANO;
683 u64 n = priv->dsiclk / 4 * priv->dsi_lanes;
684
685 return (u32)div_u64(m, n);
686 }
687
tc358768_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)688 static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge,
689 struct drm_atomic_state *state)
690 {
691 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
692 struct mipi_dsi_device *dsi_dev = priv->output.dev;
693 unsigned long mode_flags = dsi_dev->mode_flags;
694 u32 val, val2, lptxcnt, hact, data_type;
695 s32 raw_val;
696 struct drm_crtc_state *crtc_state;
697 struct drm_connector_state *conn_state;
698 struct drm_connector *connector;
699 const struct drm_display_mode *mode;
700 u32 hsbyteclk_ps, dsiclk_ps, ui_ps;
701 u32 dsiclk, hsbyteclk;
702 int ret, i;
703 struct videomode vm;
704 struct device *dev = priv->dev;
705 /* In pixelclock units */
706 u32 dpi_htot, dpi_data_start;
707 /* In byte units */
708 u32 dsi_dpi_htot, dsi_dpi_data_start;
709 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp;
710 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */
711 /* In hsbyteclk units */
712 u32 dsi_vsdly;
713 const u32 internal_dly = 40;
714
715 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
716 dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n");
717 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
718 }
719
720 tc358768_hw_enable(priv);
721
722 ret = tc358768_sw_reset(priv);
723 if (ret) {
724 dev_err(dev, "Software reset failed: %d\n", ret);
725 tc358768_hw_disable(priv);
726 return;
727 }
728
729 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
730 conn_state = drm_atomic_get_new_connector_state(state, connector);
731 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
732 mode = &crtc_state->adjusted_mode;
733 ret = tc358768_setup_pll(priv, mode);
734 if (ret) {
735 dev_err(dev, "PLL setup failed: %d\n", ret);
736 tc358768_hw_disable(priv);
737 return;
738 }
739
740 drm_display_mode_to_videomode(mode, &vm);
741
742 dsiclk = priv->dsiclk;
743 hsbyteclk = dsiclk / 4;
744
745 /* Data Format Control Register */
746 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
747 switch (dsi_dev->format) {
748 case MIPI_DSI_FMT_RGB888:
749 val |= (0x3 << 4);
750 hact = vm.hactive * 3;
751 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
752 break;
753 case MIPI_DSI_FMT_RGB666:
754 val |= (0x4 << 4);
755 hact = vm.hactive * 3;
756 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
757 break;
758
759 case MIPI_DSI_FMT_RGB666_PACKED:
760 val |= (0x4 << 4) | BIT(3);
761 hact = vm.hactive * 18 / 8;
762 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
763 break;
764
765 case MIPI_DSI_FMT_RGB565:
766 val |= (0x5 << 4);
767 hact = vm.hactive * 2;
768 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
769 break;
770 default:
771 dev_err(dev, "Invalid data format (%u)\n",
772 dsi_dev->format);
773 tc358768_hw_disable(priv);
774 return;
775 }
776
777 /*
778 * There are three important things to make TC358768 work correctly,
779 * which are not trivial to manage:
780 *
781 * 1. Keep the DPI line-time and the DSI line-time as close to each
782 * other as possible.
783 * 2. TC358768 goes to LP mode after each line's active area. The DSI
784 * HFP period has to be long enough for entering and exiting LP mode.
785 * But it is not clear how to calculate this.
786 * 3. VSDly (video start delay) has to be long enough to ensure that the
787 * DSI TX does not start transmitting until we have started receiving
788 * pixel data from the DPI input. It is not clear how to calculate
789 * this either.
790 */
791
792 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch;
793 dpi_data_start = vm.hsync_len + vm.hback_porch;
794
795 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n",
796 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch,
797 dpi_htot);
798
799 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n",
800 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
801 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
802 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock),
803 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock),
804 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock));
805
806 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n",
807 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock),
808 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock),
809 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock));
810
811 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot);
812 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start);
813
814 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
815 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len);
816 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch);
817 } else {
818 /* HBP is included in HSW in event mode */
819 dsi_hbp = 0;
820 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv,
821 vm.hsync_len +
822 vm.hback_porch);
823
824 /*
825 * The pixel packet includes the actual pixel data, and:
826 * DSI packet header = 4 bytes
827 * DCS code = 1 byte
828 * DSI packet footer = 2 bytes
829 */
830 dsi_hact = hact + 4 + 1 + 2;
831
832 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
833
834 /*
835 * Here we should check if HFP is long enough for entering LP
836 * and exiting LP, but it's not clear how to calculate that.
837 * Instead, this is a naive algorithm that just adjusts the HFP
838 * and HSW so that HFP is (at least) roughly 2/3 of the total
839 * blanking time.
840 */
841 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) {
842 u32 old_hfp = dsi_hfp;
843 u32 old_hsw = dsi_hsw;
844 u32 tot = dsi_hfp + dsi_hsw + dsi_hss;
845
846 dsi_hsw = tot / 3;
847
848 /*
849 * Seems like sometimes HSW has to be divisible by num-lanes, but
850 * not always...
851 */
852 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes);
853
854 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss;
855
856 dev_dbg(dev,
857 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n",
858 old_hfp, old_hsw, dsi_hfp, dsi_hsw);
859 }
860
861 dev_dbg(dev,
862 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n",
863 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp,
864 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp);
865
866 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n",
867 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
868 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
869 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
870 tc358768_dsi_bytes_to_ns(priv, dsi_hact),
871 tc358768_dsi_bytes_to_ns(priv, dsi_hfp),
872 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw +
873 dsi_hbp + dsi_hact + dsi_hfp));
874 }
875
876 /* VSDly calculation */
877
878 /* Start with the HW internal delay */
879 dsi_vsdly = internal_dly;
880
881 /* Convert to byte units as the other variables are in byte units */
882 dsi_vsdly *= priv->dsi_lanes;
883
884 /* Do we need more delay, in addition to the internal? */
885 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) {
886 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp;
887 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes);
888 }
889
890 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n",
891 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp,
892 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp);
893
894 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n",
895 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly),
896 tc358768_dsi_bytes_to_ns(priv, dsi_hss),
897 tc358768_dsi_bytes_to_ns(priv, dsi_hsw),
898 tc358768_dsi_bytes_to_ns(priv, dsi_hbp),
899 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp));
900
901 /* Convert back to hsbyteclk */
902 dsi_vsdly /= priv->dsi_lanes;
903
904 /*
905 * The docs say that there is an internal delay of 40 cycles.
906 * However, we get underflows if we follow that rule. If we
907 * instead ignore the internal delay, things work. So either
908 * the docs are wrong or the calculations are wrong.
909 *
910 * As a temporary fix, add the internal delay here, to counter
911 * the subtraction when writing the register.
912 */
913 dsi_vsdly += internal_dly;
914
915 /* Clamp to the register max */
916 if (dsi_vsdly - internal_dly > 0x3ff) {
917 dev_warn(dev, "VSDly too high, underflows likely\n");
918 dsi_vsdly = 0x3ff + internal_dly;
919 }
920
921 /* VSDly[9:0] */
922 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly);
923
924 tc358768_write(priv, TC358768_DATAFMT, val);
925 tc358768_write(priv, TC358768_DSITX_DT, data_type);
926
927 /* Enable D-PHY (HiZ->LP11) */
928 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
929 /* Enable lanes */
930 for (i = 0; i < dsi_dev->lanes; i++)
931 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
932
933 /* DSI Timings */
934 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk);
935 dsiclk_ps = (u32)div_u64(PICO, dsiclk);
936 ui_ps = dsiclk_ps / 2;
937 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps,
938 ui_ps, hsbyteclk_ps);
939
940 /* LP11 > 100us for D-PHY Rx Init */
941 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1;
942 dev_dbg(dev, "LINEINITCNT: %u\n", val);
943 tc358768_write(priv, TC358768_LINEINITCNT, val);
944
945 /* LPTimeCnt > 50ns */
946 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1;
947 lptxcnt = val;
948 dev_dbg(dev, "LPTXTIMECNT: %u\n", val);
949 tc358768_write(priv, TC358768_LPTXTIMECNT, val);
950
951 /* 38ns < TCLK_PREPARE < 95ns */
952 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1;
953 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val);
954 /* TCLK_PREPARE + TCLK_ZERO > 300ns */
955 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps),
956 hsbyteclk_ps) - 2;
957 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2);
958 val |= val2 << 8;
959 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
960
961 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
962 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5;
963 val = clamp(raw_val, 0, 127);
964 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val);
965 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
966
967 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
968 val = 50 + tc358768_ps_to_ns(4 * ui_ps);
969 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1;
970 dev_dbg(dev, "THS_PREPARECNT %u\n", val);
971 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
972 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10;
973 val2 = clamp(raw_val, 0, 127);
974 dev_dbg(dev, "THS_ZEROCNT %u\n", val2);
975 val |= val2 << 8;
976 tc358768_write(priv, TC358768_THS_HEADERCNT, val);
977
978 /* TWAKEUP > 1ms in lptxcnt steps */
979 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps);
980 val = val / (lptxcnt + 1) - 1;
981 dev_dbg(dev, "TWAKEUP: %u\n", val);
982 tc358768_write(priv, TC358768_TWAKEUP, val);
983
984 /* TCLK_POSTCNT > 60ns + 52*UI */
985 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps),
986 hsbyteclk_ps) - 3;
987 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val);
988 tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
989
990 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
991 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps),
992 hsbyteclk_ps) - 4;
993 val = clamp(raw_val, 0, 15);
994 dev_dbg(dev, "THS_TRAILCNT: %u\n", val);
995 tc358768_write(priv, TC358768_THS_TRAILCNT, val);
996
997 val = BIT(0);
998 for (i = 0; i < dsi_dev->lanes; i++)
999 val |= BIT(i + 1);
1000 tc358768_write(priv, TC358768_HSTXVREGEN, val);
1001
1002 tc358768_write(priv, TC358768_TXOPTIONCNTRL,
1003 (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
1004
1005 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
1006 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4);
1007 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1;
1008 dev_dbg(dev, "TXTAGOCNT: %u\n", val);
1009 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps),
1010 hsbyteclk_ps) - 2;
1011 dev_dbg(dev, "RXTASURECNT: %u\n", val2);
1012 val = val << 16 | val2;
1013 tc358768_write(priv, TC358768_BTACNTRL1, val);
1014
1015 /* START[0] */
1016 tc358768_write(priv, TC358768_STARTCNTRL, 1);
1017
1018 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
1019 /* Set pulse mode */
1020 tc358768_write(priv, TC358768_DSI_EVENT, 0);
1021
1022 /* vact */
1023 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1024
1025 /* vsw */
1026 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len);
1027
1028 /* vbp */
1029 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch);
1030 } else {
1031 /* Set event mode */
1032 tc358768_write(priv, TC358768_DSI_EVENT, 1);
1033
1034 /* vact */
1035 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive);
1036
1037 /* vsw (+ vbp) */
1038 tc358768_write(priv, TC358768_DSI_VSW,
1039 vm.vsync_len + vm.vback_porch);
1040
1041 /* vbp (not used in event mode) */
1042 tc358768_write(priv, TC358768_DSI_VBPR, 0);
1043 }
1044
1045 /* hsw (bytes) */
1046 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw);
1047
1048 /* hbp (bytes) */
1049 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp);
1050
1051 /* hact (bytes) */
1052 tc358768_write(priv, TC358768_DSI_HACT, hact);
1053
1054 /* VSYNC polarity */
1055 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
1056 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
1057
1058 /* HSYNC polarity */
1059 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
1060 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
1061
1062 /* Start DSI Tx */
1063 tc358768_write(priv, TC358768_DSI_START, 0x1);
1064
1065 /* Configure DSI_Control register */
1066 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1067 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
1068 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
1069 tc358768_write(priv, TC358768_DSI_CONFW, val);
1070
1071 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1072 val |= (dsi_dev->lanes - 1) << 1;
1073
1074 val |= TC358768_DSI_CONTROL_TXMD;
1075
1076 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
1077 val |= TC358768_DSI_CONTROL_HSCKMD;
1078
1079 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
1080 val |= TC358768_DSI_CONTROL_EOTDIS;
1081
1082 tc358768_write(priv, TC358768_DSI_CONFW, val);
1083
1084 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
1085 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
1086 tc358768_write(priv, TC358768_DSI_CONFW, val);
1087
1088 ret = tc358768_clear_error(priv);
1089 if (ret)
1090 dev_err(dev, "Bridge pre_enable failed: %d\n", ret);
1091 }
1092
tc358768_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1093 static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge,
1094 struct drm_atomic_state *state)
1095 {
1096 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1097 int ret;
1098
1099 if (!priv->enabled) {
1100 dev_err(priv->dev, "Bridge is not enabled\n");
1101 return;
1102 }
1103
1104 /* clear FrmStop and RstPtr */
1105 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
1106
1107 /* set PP_en */
1108 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
1109
1110 ret = tc358768_clear_error(priv);
1111 if (ret)
1112 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
1113 }
1114
1115 #define MAX_INPUT_SEL_FORMATS 1
1116
1117 static u32 *
tc358768_atomic_get_input_bus_fmts(struct drm_bridge * bridge,struct drm_bridge_state * bridge_state,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state,u32 output_fmt,unsigned int * num_input_fmts)1118 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1119 struct drm_bridge_state *bridge_state,
1120 struct drm_crtc_state *crtc_state,
1121 struct drm_connector_state *conn_state,
1122 u32 output_fmt,
1123 unsigned int *num_input_fmts)
1124 {
1125 struct tc358768_priv *priv = bridge_to_tc358768(bridge);
1126 u32 *input_fmts;
1127
1128 *num_input_fmts = 0;
1129
1130 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
1131 GFP_KERNEL);
1132 if (!input_fmts)
1133 return NULL;
1134
1135 switch (priv->pd_lines) {
1136 case 16:
1137 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
1138 break;
1139 case 18:
1140 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
1141 break;
1142 default:
1143 case 24:
1144 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
1145 break;
1146 }
1147
1148 *num_input_fmts = MAX_INPUT_SEL_FORMATS;
1149
1150 return input_fmts;
1151 }
1152
tc358768_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1153 static bool tc358768_mode_fixup(struct drm_bridge *bridge,
1154 const struct drm_display_mode *mode,
1155 struct drm_display_mode *adjusted_mode)
1156 {
1157 /* Default to positive sync */
1158
1159 if (!(adjusted_mode->flags &
1160 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
1161 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
1162
1163 if (!(adjusted_mode->flags &
1164 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
1165 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC;
1166
1167 return true;
1168 }
1169
1170 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
1171 .attach = tc358768_bridge_attach,
1172 .mode_valid = tc358768_bridge_mode_valid,
1173 .mode_fixup = tc358768_mode_fixup,
1174 .atomic_pre_enable = tc358768_bridge_atomic_pre_enable,
1175 .atomic_enable = tc358768_bridge_atomic_enable,
1176 .atomic_disable = tc358768_bridge_atomic_disable,
1177 .atomic_post_disable = tc358768_bridge_atomic_post_disable,
1178
1179 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1180 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1181 .atomic_reset = drm_atomic_helper_bridge_reset,
1182 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
1183 };
1184
1185 static const struct drm_bridge_timings default_tc358768_timings = {
1186 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
1187 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
1188 | DRM_BUS_FLAG_DE_HIGH,
1189 };
1190
tc358768_is_reserved_reg(unsigned int reg)1191 static bool tc358768_is_reserved_reg(unsigned int reg)
1192 {
1193 switch (reg) {
1194 case 0x114 ... 0x13f:
1195 case 0x200:
1196 case 0x20c:
1197 case 0x400 ... 0x408:
1198 case 0x41c ... 0x42f:
1199 return true;
1200 default:
1201 return false;
1202 }
1203 }
1204
tc358768_writeable_reg(struct device * dev,unsigned int reg)1205 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
1206 {
1207 if (tc358768_is_reserved_reg(reg))
1208 return false;
1209
1210 switch (reg) {
1211 case TC358768_CHIPID:
1212 case TC358768_FIFOSTATUS:
1213 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
1214 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
1215 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
1216 return false;
1217 default:
1218 return true;
1219 }
1220 }
1221
tc358768_readable_reg(struct device * dev,unsigned int reg)1222 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
1223 {
1224 if (tc358768_is_reserved_reg(reg))
1225 return false;
1226
1227 switch (reg) {
1228 case TC358768_STARTCNTRL:
1229 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
1230 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
1231 case TC358768_DSI_START ... (TC358768_DSI_START + 2):
1232 case TC358768_DBG_DATA:
1233 return false;
1234 default:
1235 return true;
1236 }
1237 }
1238
1239 static const struct regmap_config tc358768_regmap_config = {
1240 .name = "tc358768",
1241 .reg_bits = 16,
1242 .val_bits = 16,
1243 .max_register = TC358768_DSI_HACT,
1244 .cache_type = REGCACHE_NONE,
1245 .writeable_reg = tc358768_writeable_reg,
1246 .readable_reg = tc358768_readable_reg,
1247 .reg_format_endian = REGMAP_ENDIAN_BIG,
1248 .val_format_endian = REGMAP_ENDIAN_BIG,
1249 };
1250
1251 static const struct i2c_device_id tc358768_i2c_ids[] = {
1252 { "tc358768" },
1253 { "tc358778" },
1254 { }
1255 };
1256 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1257
1258 static const struct of_device_id tc358768_of_ids[] = {
1259 { .compatible = "toshiba,tc358768", },
1260 { .compatible = "toshiba,tc358778", },
1261 { }
1262 };
1263 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1264
tc358768_get_regulators(struct tc358768_priv * priv)1265 static int tc358768_get_regulators(struct tc358768_priv *priv)
1266 {
1267 int i, ret;
1268
1269 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1270 priv->supplies[i].supply = tc358768_supplies[i];
1271
1272 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1273 priv->supplies);
1274 if (ret < 0)
1275 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1276
1277 return ret;
1278 }
1279
tc358768_i2c_probe(struct i2c_client * client)1280 static int tc358768_i2c_probe(struct i2c_client *client)
1281 {
1282 struct tc358768_priv *priv;
1283 struct device *dev = &client->dev;
1284 struct device_node *np = dev->of_node;
1285 int ret;
1286
1287 if (!np)
1288 return -ENODEV;
1289
1290 priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge,
1291 &tc358768_bridge_funcs);
1292 if (IS_ERR(priv))
1293 return PTR_ERR(priv);
1294
1295 dev_set_drvdata(dev, priv);
1296 priv->dev = dev;
1297
1298 ret = tc358768_get_regulators(priv);
1299 if (ret)
1300 return ret;
1301
1302 priv->refclk = devm_clk_get(dev, "refclk");
1303 if (IS_ERR(priv->refclk))
1304 return PTR_ERR(priv->refclk);
1305
1306 /*
1307 * RESX is low active, to disable tc358768 initially (keep in reset)
1308 * the gpio line must be LOW. This is the ASSERTED state of
1309 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1310 */
1311 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1312 GPIOD_OUT_HIGH);
1313 if (IS_ERR(priv->reset_gpio))
1314 return PTR_ERR(priv->reset_gpio);
1315
1316 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1317 if (IS_ERR(priv->regmap)) {
1318 dev_err(dev, "Failed to init regmap\n");
1319 return PTR_ERR(priv->regmap);
1320 }
1321
1322 priv->dsi_host.dev = dev;
1323 priv->dsi_host.ops = &tc358768_dsi_host_ops;
1324
1325 priv->bridge.timings = &default_tc358768_timings;
1326 priv->bridge.of_node = np;
1327
1328 i2c_set_clientdata(client, priv);
1329
1330 return mipi_dsi_host_register(&priv->dsi_host);
1331 }
1332
tc358768_i2c_remove(struct i2c_client * client)1333 static void tc358768_i2c_remove(struct i2c_client *client)
1334 {
1335 struct tc358768_priv *priv = i2c_get_clientdata(client);
1336
1337 mipi_dsi_host_unregister(&priv->dsi_host);
1338 }
1339
1340 static struct i2c_driver tc358768_driver = {
1341 .driver = {
1342 .name = "tc358768",
1343 .of_match_table = tc358768_of_ids,
1344 },
1345 .id_table = tc358768_i2c_ids,
1346 .probe = tc358768_i2c_probe,
1347 .remove = tc358768_i2c_remove,
1348 };
1349 module_i2c_driver(tc358768_driver);
1350
1351 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1352 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1353 MODULE_LICENSE("GPL v2");
1354