Searched refs:SR_INT (Results 1 – 3 of 3) sorted by relevance
87 #define SR_INT 0x04 /* Shift register full/empty */ macro 272 out_8(&via[IER], IER_SET|SR_INT); /* enable interrupt from SR */ in find_via_cuda() 357 if (in_8(&via[IFR]) & SR_INT) in sync_egret() 381 out_8(&via[IER], SR_INT); /* disable SR interrupt from VIA */ in cuda_init_via() 396 out_8(&via[IFR], SR_INT); in cuda_init_via() 405 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (2)"); in cuda_init_via() 407 out_8(&via[IFR], SR_INT); in cuda_init_via() 414 WAIT_FOR(in_8(&via[IFR]) & SR_INT, "CUDA response to sync (4)"); in cuda_init_via() 416 out_8(&via[IFR], SR_INT); in cuda_init_via() 583 if ((in_8(&via[IFR]) & SR_INT) in cuda_interrupt() [all...]
70 #define SR_INT 0x04 /* Shift register full/empty */ macro 350 * generating shift register interrupts (SR_INT) for us. This means there has355 * register which eventually raises the SR_INT interrupt. The PB4/PB5 outputs375 if (via[IFR] & SR_INT) in macii_interrupt() 376 via[IFR] = SR_INT; in macii_interrupt()
118 #define SR_INT 0x04 /* Shift register full/empty */ macro 465 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in via_pmu_start() 1592 intr = in_8(&via1[IFR]) & (SR_INT | CB1_INT); in via_pmu_interrupt() 1601 intr = SR_INT; in via_pmu_interrupt() 1618 if (intr & SR_INT) { in via_pmu_interrupt() 1854 out_8(&via1[IER], IER_SET | SR_INT | CB1_INT); in restore_via_state()