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Searched refs:SOFT_SCRATCH (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc.c212 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0)); in intel_guc_init_early()
387 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and in intel_guc_write_params()
393 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0); in intel_guc_write_params()
396 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]); in intel_guc_write_params()
944 i, intel_uncore_read(uncore, SOFT_SCRATCH(i))); in intel_guc_load_status()
H A Dintel_guc_reg.h35 #define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4) macro
H A Dintel_guc_fw.c236 intel_uncore_read(uncore, SOFT_SCRATCH(13))); in guc_wait_ucode()
H A Dintel_uc.c185 intel_uncore_write(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15), 0); in guc_clear_mmio_msg()
194 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15)); in guc_get_mmio_msg()
/linux/drivers/gpu/drm/xe/
H A Dxe_guc.c280 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(0), 0); in guc_write_params()
283 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); in guc_write_params()
1141 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); in guc_wait_ucode()
1289 msg = xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(15)); in guc_handle_mmio_msg()
1292 xe_mmio_write32(&gt->mmio, SOFT_SCRATCH(15), 0); in guc_handle_mmio_msg()
1647 i, xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(i))); in xe_guc_print_info()
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_guc_regs.h60 #define SOFT_SCRATCH(n) XE_REG(0xc180 + (n) * 4) macro
/linux/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c1135 MMIO_F(SOFT_SCRATCH(0), 16 * 4); in iterate_bxt_mmio()