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Searched refs:RREG32_PCIE (Results 1 – 25 of 37) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c168 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
196 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
217 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
222 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
266 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v6_1_init_registers()
273 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
287 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v6_1_program_ltr()
292 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); in nbio_v6_1_program_ltr()
297 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v6_1_program_ltr()
309 def = data = RREG32_PCIE(smnPCIE_LC_CNT in nbio_v6_1_program_aspm()
[all...]
H A Dnbio_v2_3.c236 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
265 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
286 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
291 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
335 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL); in nbio_v2_3_init_registers()
352 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_enable_aspm()
391 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL); in nbio_v2_3_program_ltr()
396 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); in nbio_v2_3_program_ltr()
408 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
415 def = data = RREG32_PCIE(smnPCIE_LC_CNTL in nbio_v2_3_program_aspm()
[all...]
H A Dumc_v6_1.c50 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_enable_umc_index_mode()
65 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_disable_umc_index_mode()
80 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_get_umc_index_mode_state()
119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
197 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
202 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
212 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
412 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_err_cnt_init_per_channel()
H A Dcik.c1550 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1580 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1587 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in cik_pcie_gen3_enable()
1620 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1624 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1654 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1677 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1682 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); in cik_pcie_gen3_enable()
1701 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1708 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL in cik_program_aspm()
[all...]
H A Dvi.c1110 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_enable_aspm()
1133 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_program_aspm()
1140 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in vi_program_aspm()
1147 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in vi_program_aspm()
1152 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in vi_program_aspm()
1157 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE); in vi_program_aspm()
1172 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6); in vi_program_aspm()
1177 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); in vi_program_aspm()
1219 orig = data = RREG32_PCIE(ixCPM_CONTROL); in vi_program_aspm()
1225 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNT in vi_program_aspm()
[all...]
H A Dumc_v8_14.c71 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_correctable_error_count()
86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_uncorrectable_error_count()
133 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_14_err_cnt_init_per_channel()
H A Dumc_v8_7.c192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
257 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
267 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
402 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
H A Dnbio_v7_0.c153 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
191 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
212 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
217 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
H A Damdgpu_xgmi.c1415 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1422 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1431 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1438 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1447 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1449 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1456 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1458 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1474 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1476 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_ in amdgpu_xgmi_legacy_query_ras_error_count()
[all...]
H A Dsi.c1632 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1637 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1638 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1646 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1647 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
2286 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in si_pcie_gen3_enable()
2447 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in si_program_aspm()
2610 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in si_program_aspm()
2618 data = RREG32_PCIE(ixPCIE_LC_STATUS1); in si_program_aspm()
H A Dpsp_v3_1.c303 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
H A Damdgpu_cgs.c64 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
H A Dumc_v8_10.c308 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel()
H A Dgmc_v6_0.c705 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v6_0_enable_bif_mgls()
H A Daqua_vanjaram.c579 regdata->value = RREG32_PCIE(smn_addr); in aqua_read_smn()
/linux/drivers/gpu/drm/radeon/
H A Dr300.c94 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
96 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
179 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
199 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
538 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
554 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
556 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_set_pcie_lanes()
572 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); in rv370_get_pcie_lanes()
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BAS in rv370_debugfs_pcie_gart_info_show()
[all...]
H A Dsi.c5552 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
7122 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7247 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
7410 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7418 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
H A Dvega20_smumgr.c54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c171 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_load_microcode()
245 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
249 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
1961 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
1981 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_get_current_pcie_link_speed_level()
2447 ret = RREG32_PCIE(MP1_Public | in smu_v13_0_disable_pmfw_state()
H A Dsmu_v13_0_6_ppt.c1094 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu_v13_0_6_check_fw_status()
2533 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL), in smu_v13_0_6_get_current_pcie_link_width_level()
2544 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); in smu_v13_0_6_get_current_pcie_link_speed()
2548 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_6_get_current_pcie_link_speed()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c146 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_load_microcode()
149 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_load_microcode()
219 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_check_fw_status()
222 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_check_fw_status()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c166 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
185 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
2066 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
2086 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v11_0_get_current_pcie_link_speed_level()
H A Dsienna_cichlid_ppt.c3002 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_START); in sienna_cichlid_stb_init()
3012 reg = RREG32_PCIE(MP1_Public | smnMP1_PMI_3_FIFO); in sienna_cichlid_stb_init()
3089 *p++ = cpu_to_le32(RREG32_PCIE(MP1_Public | smnMP1_PMI_3)); in sienna_cichlid_stb_get_data_direct()

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