1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2L SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g054-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g054"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 cache-level = <3>; 113 }; 114 }; 115 116 gpu_opp_table: opp-table-1 { 117 compatible = "operating-points-v2"; 118 119 opp-500000000 { 120 opp-hz = /bits/ 64 <500000000>; 121 opp-microvolt = <1100000>; 122 }; 123 124 opp-400000000 { 125 opp-hz = /bits/ 64 <400000000>; 126 opp-microvolt = <1100000>; 127 }; 128 129 opp-250000000 { 130 opp-hz = /bits/ 64 <250000000>; 131 opp-microvolt = <1100000>; 132 }; 133 134 opp-200000000 { 135 opp-hz = /bits/ 64 <200000000>; 136 opp-microvolt = <1100000>; 137 }; 138 139 opp-125000000 { 140 opp-hz = /bits/ 64 <125000000>; 141 opp-microvolt = <1100000>; 142 }; 143 144 opp-100000000 { 145 opp-hz = /bits/ 64 <100000000>; 146 opp-microvolt = <1100000>; 147 }; 148 149 opp-62500000 { 150 opp-hz = /bits/ 64 <62500000>; 151 opp-microvolt = <1100000>; 152 }; 153 154 opp-50000000 { 155 opp-hz = /bits/ 64 <50000000>; 156 opp-microvolt = <1100000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a55-pmu"; 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 163 }; 164 165 psci { 166 compatible = "arm,psci-1.0", "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 soc: soc { 171 compatible = "simple-bus"; 172 interrupt-parent = <&gic>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 177 mtu3: timer@10001200 { 178 compatible = "renesas,r9a07g054-mtu3", 179 "renesas,rz-mtu3"; 180 reg = <0 0x10001200 0 0xb00>; 181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, 185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, 188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, 193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, 196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, 197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, 198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, 202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, 203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, 207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, 208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, 210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, 212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, 213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, 214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, 216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, 217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, 218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", 226 "tciv0", "tgie0", "tgif0", 227 "tgia1", "tgib1", "tciv1", "tciu1", 228 "tgia2", "tgib2", "tciv2", "tciu2", 229 "tgia3", "tgib3", "tgic3", "tgid3", 230 "tciv3", 231 "tgia4", "tgib4", "tgic4", "tgid4", 232 "tciv4", 233 "tgiu5", "tgiv5", "tgiw5", 234 "tgia6", "tgib6", "tgic6", "tgid6", 235 "tciv6", 236 "tgia7", "tgib7", "tgic7", "tgid7", 237 "tciv7", 238 "tgia8", "tgib8", "tgic8", "tgid8", 239 "tciv8", "tciu8"; 240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>; 241 power-domains = <&cpg>; 242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>; 243 #pwm-cells = <2>; 244 status = "disabled"; 245 }; 246 247 gpt: pwm@10048000 { 248 compatible = "renesas,r9a07g054-gpt", 249 "renesas,rzg2l-gpt"; 250 reg = <0 0x10048000 0 0x800>; 251 #pwm-cells = <3>; 252 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>, 261 <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>, 262 <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>, 263 <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, 264 <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>, 265 <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>, 266 <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>, 267 <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>, 268 <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>, 269 <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>, 270 <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>, 271 <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>, 272 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 273 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>, 274 <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>, 275 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 276 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 277 <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>, 278 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 279 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>, 280 <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>, 283 <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>, 284 <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>, 285 <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>, 286 <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 290 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 291 <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 292 <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 294 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 295 <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>, 297 <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>, 298 <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>, 299 <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>, 300 <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>, 301 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 302 <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>, 303 <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>, 304 <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>, 305 <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>, 306 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 307 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>, 311 <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 332 interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0", 333 "cmpe0", "cmpf0", "adtrga0", "adtrgb0", 334 "ovf0", "unf0", 335 "ccmpa1", "ccmpb1", "cmpc1", "cmpd1", 336 "cmpe1", "cmpf1", "adtrga1", "adtrgb1", 337 "ovf1", "unf1", 338 "ccmpa2", "ccmpb2", "cmpc2", "cmpd2", 339 "cmpe2", "cmpf2", "adtrga2", "adtrgb2", 340 "ovf2", "unf2", 341 "ccmpa3", "ccmpb3", "cmpc3", "cmpd3", 342 "cmpe3", "cmpf3", "adtrga3", "adtrgb3", 343 "ovf3", "unf3", 344 "ccmpa4", "ccmpb4", "cmpc4", "cmpd4", 345 "cmpe4", "cmpf4", "adtrga4", "adtrgb4", 346 "ovf4", "unf4", 347 "ccmpa5", "ccmpb5", "cmpc5", "cmpd5", 348 "cmpe5", "cmpf5", "adtrga5", "adtrgb5", 349 "ovf5", "unf5", 350 "ccmpa6", "ccmpb6", "cmpc6", "cmpd6", 351 "cmpe6", "cmpf6", "adtrga6", "adtrgb6", 352 "ovf6", "unf6", 353 "ccmpa7", "ccmpb7", "cmpc7", "cmpd7", 354 "cmpe7", "cmpf7", "adtrga7", "adtrgb7", 355 "ovf7", "unf7"; 356 clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>; 357 resets = <&cpg R9A07G054_GPT_RST_C>; 358 power-domains = <&cpg>; 359 status = "disabled"; 360 }; 361 362 ssi0: ssi@10049c00 { 363 compatible = "renesas,r9a07g054-ssi", 364 "renesas,rz-ssi"; 365 reg = <0 0x10049c00 0 0x400>; 366 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 368 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; 369 interrupt-names = "int_req", "dma_rx", "dma_tx"; 370 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, 371 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, 372 <&audio_clk1>, <&audio_clk2>; 373 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 374 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; 375 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 376 dma-names = "tx", "rx"; 377 power-domains = <&cpg>; 378 #sound-dai-cells = <0>; 379 status = "disabled"; 380 }; 381 382 ssi1: ssi@1004a000 { 383 compatible = "renesas,r9a07g054-ssi", 384 "renesas,rz-ssi"; 385 reg = <0 0x1004a000 0 0x400>; 386 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; 389 interrupt-names = "int_req", "dma_rx", "dma_tx"; 390 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, 391 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, 392 <&audio_clk1>, <&audio_clk2>; 393 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 394 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; 395 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 396 dma-names = "tx", "rx"; 397 power-domains = <&cpg>; 398 #sound-dai-cells = <0>; 399 status = "disabled"; 400 }; 401 402 ssi2: ssi@1004a400 { 403 compatible = "renesas,r9a07g054-ssi", 404 "renesas,rz-ssi"; 405 reg = <0 0x1004a400 0 0x400>; 406 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 408 interrupt-names = "int_req", "dma_rt"; 409 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, 410 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, 411 <&audio_clk1>, <&audio_clk2>; 412 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 413 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; 414 dmas = <&dmac 0x265f>; 415 dma-names = "rt"; 416 power-domains = <&cpg>; 417 #sound-dai-cells = <0>; 418 status = "disabled"; 419 }; 420 421 ssi3: ssi@1004a800 { 422 compatible = "renesas,r9a07g054-ssi", 423 "renesas,rz-ssi"; 424 reg = <0 0x1004a800 0 0x400>; 425 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 428 interrupt-names = "int_req", "dma_rx", "dma_tx"; 429 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, 430 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, 431 <&audio_clk1>, <&audio_clk2>; 432 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 433 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; 434 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 435 dma-names = "tx", "rx"; 436 power-domains = <&cpg>; 437 #sound-dai-cells = <0>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@1004ac00 { 442 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 443 reg = <0 0x1004ac00 0 0x400>; 444 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 447 interrupt-names = "error", "rx", "tx"; 448 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; 449 resets = <&cpg R9A07G054_RSPI0_RST>; 450 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 451 dma-names = "tx", "rx"; 452 power-domains = <&cpg>; 453 num-cs = <1>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 }; 458 459 spi1: spi@1004b000 { 460 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 461 reg = <0 0x1004b000 0 0x400>; 462 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "error", "rx", "tx"; 466 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; 467 resets = <&cpg R9A07G054_RSPI1_RST>; 468 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 469 dma-names = "tx", "rx"; 470 power-domains = <&cpg>; 471 num-cs = <1>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 status = "disabled"; 475 }; 476 477 spi2: spi@1004b400 { 478 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; 479 reg = <0 0x1004b400 0 0x400>; 480 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "error", "rx", "tx"; 484 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; 485 resets = <&cpg R9A07G054_RSPI2_RST>; 486 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 487 dma-names = "tx", "rx"; 488 power-domains = <&cpg>; 489 num-cs = <1>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 status = "disabled"; 493 }; 494 495 scif0: serial@1004b800 { 496 compatible = "renesas,scif-r9a07g054", 497 "renesas,scif-r9a07g044"; 498 reg = <0 0x1004b800 0 0x400>; 499 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "eri", "rxi", "txi", 506 "bri", "dri", "tei"; 507 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; 508 clock-names = "fck"; 509 power-domains = <&cpg>; 510 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; 511 status = "disabled"; 512 }; 513 514 scif1: serial@1004bc00 { 515 compatible = "renesas,scif-r9a07g054", 516 "renesas,scif-r9a07g044"; 517 reg = <0 0x1004bc00 0 0x400>; 518 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 524 interrupt-names = "eri", "rxi", "txi", 525 "bri", "dri", "tei"; 526 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; 527 clock-names = "fck"; 528 power-domains = <&cpg>; 529 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; 530 status = "disabled"; 531 }; 532 533 scif2: serial@1004c000 { 534 compatible = "renesas,scif-r9a07g054", 535 "renesas,scif-r9a07g044"; 536 reg = <0 0x1004c000 0 0x400>; 537 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 543 interrupt-names = "eri", "rxi", "txi", 544 "bri", "dri", "tei"; 545 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; 546 clock-names = "fck"; 547 power-domains = <&cpg>; 548 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; 549 status = "disabled"; 550 }; 551 552 scif3: serial@1004c400 { 553 compatible = "renesas,scif-r9a07g054", 554 "renesas,scif-r9a07g044"; 555 reg = <0 0x1004c400 0 0x400>; 556 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "eri", "rxi", "txi", 563 "bri", "dri", "tei"; 564 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; 565 clock-names = "fck"; 566 power-domains = <&cpg>; 567 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; 568 status = "disabled"; 569 }; 570 571 scif4: serial@1004c800 { 572 compatible = "renesas,scif-r9a07g054", 573 "renesas,scif-r9a07g044"; 574 reg = <0 0x1004c800 0 0x400>; 575 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 581 interrupt-names = "eri", "rxi", "txi", 582 "bri", "dri", "tei"; 583 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; 584 clock-names = "fck"; 585 power-domains = <&cpg>; 586 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; 587 status = "disabled"; 588 }; 589 590 sci0: serial@1004d000 { 591 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 592 reg = <0 0x1004d000 0 0x400>; 593 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 595 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 596 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 597 interrupt-names = "eri", "rxi", "txi", "tei"; 598 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; 599 clock-names = "fck"; 600 power-domains = <&cpg>; 601 resets = <&cpg R9A07G054_SCI0_RST>; 602 status = "disabled"; 603 }; 604 605 sci1: serial@1004d400 { 606 compatible = "renesas,r9a07g054-sci", "renesas,sci"; 607 reg = <0 0x1004d400 0 0x400>; 608 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 610 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 611 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "eri", "rxi", "txi", "tei"; 613 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; 614 clock-names = "fck"; 615 power-domains = <&cpg>; 616 resets = <&cpg R9A07G054_SCI1_RST>; 617 status = "disabled"; 618 }; 619 620 canfd: can@10050000 { 621 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; 622 reg = <0 0x10050000 0 0x8000>; 623 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "g_err", "g_recc", 632 "ch0_err", "ch0_rec", "ch0_trx", 633 "ch1_err", "ch1_rec", "ch1_trx"; 634 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, 635 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, 636 <&can_clk>; 637 clock-names = "fck", "canfd", "can_clk"; 638 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; 639 assigned-clock-rates = <50000000>; 640 resets = <&cpg R9A07G054_CANFD_RSTP_N>, 641 <&cpg R9A07G054_CANFD_RSTC_N>; 642 reset-names = "rstp_n", "rstc_n"; 643 power-domains = <&cpg>; 644 status = "disabled"; 645 646 channel0 { 647 status = "disabled"; 648 }; 649 channel1 { 650 status = "disabled"; 651 }; 652 }; 653 654 i2c0: i2c@10058000 { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 658 reg = <0 0x10058000 0 0x400>; 659 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 661 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 662 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "tei", "ri", "ti", "spi", "sti", 668 "naki", "ali", "tmoi"; 669 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; 670 clock-frequency = <100000>; 671 resets = <&cpg R9A07G054_I2C0_MRST>; 672 power-domains = <&cpg>; 673 status = "disabled"; 674 }; 675 676 i2c1: i2c@10058400 { 677 #address-cells = <1>; 678 #size-cells = <0>; 679 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 680 reg = <0 0x10058400 0 0x400>; 681 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 683 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 684 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 689 interrupt-names = "tei", "ri", "ti", "spi", "sti", 690 "naki", "ali", "tmoi"; 691 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; 692 clock-frequency = <100000>; 693 resets = <&cpg R9A07G054_I2C1_MRST>; 694 power-domains = <&cpg>; 695 status = "disabled"; 696 }; 697 698 i2c2: i2c@10058800 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 702 reg = <0 0x10058800 0 0x400>; 703 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 705 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 706 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 711 interrupt-names = "tei", "ri", "ti", "spi", "sti", 712 "naki", "ali", "tmoi"; 713 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; 714 clock-frequency = <100000>; 715 resets = <&cpg R9A07G054_I2C2_MRST>; 716 power-domains = <&cpg>; 717 status = "disabled"; 718 }; 719 720 i2c3: i2c@10058c00 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; 724 reg = <0 0x10058c00 0 0x400>; 725 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 727 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 728 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 733 interrupt-names = "tei", "ri", "ti", "spi", "sti", 734 "naki", "ali", "tmoi"; 735 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; 736 clock-frequency = <100000>; 737 resets = <&cpg R9A07G054_I2C3_MRST>; 738 power-domains = <&cpg>; 739 status = "disabled"; 740 }; 741 742 adc: adc@10059000 { 743 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; 744 reg = <0 0x10059000 0 0x400>; 745 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 746 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, 747 <&cpg CPG_MOD R9A07G054_ADC_PCLK>; 748 clock-names = "adclk", "pclk"; 749 resets = <&cpg R9A07G054_ADC_PRESETN>, 750 <&cpg R9A07G054_ADC_ADRST_N>; 751 reset-names = "presetn", "adrst-n"; 752 power-domains = <&cpg>; 753 status = "disabled"; 754 755 #address-cells = <1>; 756 #size-cells = <0>; 757 758 channel@0 { 759 reg = <0>; 760 }; 761 channel@1 { 762 reg = <1>; 763 }; 764 channel@2 { 765 reg = <2>; 766 }; 767 channel@3 { 768 reg = <3>; 769 }; 770 channel@4 { 771 reg = <4>; 772 }; 773 channel@5 { 774 reg = <5>; 775 }; 776 channel@6 { 777 reg = <6>; 778 }; 779 channel@7 { 780 reg = <7>; 781 }; 782 }; 783 784 tsu: thermal@10059400 { 785 compatible = "renesas,r9a07g054-tsu", 786 "renesas,rzg2l-tsu"; 787 reg = <0 0x10059400 0 0x400>; 788 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; 789 resets = <&cpg R9A07G054_TSU_PRESETN>; 790 power-domains = <&cpg>; 791 #thermal-sensor-cells = <1>; 792 }; 793 794 sbc: spi@10060000 { 795 compatible = "renesas,r9a07g054-rpc-if", 796 "renesas,rzg2l-rpc-if"; 797 reg = <0 0x10060000 0 0x10000>, 798 <0 0x20000000 0 0x10000000>, 799 <0 0x10070000 0 0x10000>; 800 reg-names = "regs", "dirmap", "wbuf"; 801 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, 803 <&cpg CPG_MOD R9A07G054_SPI_CLK>; 804 resets = <&cpg R9A07G054_SPI_RST>; 805 power-domains = <&cpg>; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 cru: video@10830000 { 812 compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru"; 813 reg = <0 0x10830000 0 0x400>; 814 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>, 815 <&cpg CPG_MOD R9A07G054_CRU_PCLK>, 816 <&cpg CPG_MOD R9A07G054_CRU_ACLK>; 817 clock-names = "video", "apb", "axi"; 818 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 821 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 822 resets = <&cpg R9A07G054_CRU_PRESETN>, 823 <&cpg R9A07G054_CRU_ARESETN>; 824 reset-names = "presetn", "aresetn"; 825 power-domains = <&cpg>; 826 status = "disabled"; 827 828 ports { 829 #address-cells = <1>; 830 #size-cells = <0>; 831 832 port@0 { 833 #address-cells = <1>; 834 #size-cells = <0>; 835 836 reg = <0>; 837 cruparallel: endpoint@0 { 838 reg = <0>; 839 }; 840 }; 841 842 port@1 { 843 #address-cells = <1>; 844 #size-cells = <0>; 845 846 reg = <1>; 847 crucsi2: endpoint@0 { 848 reg = <0>; 849 remote-endpoint = <&csi2cru>; 850 }; 851 }; 852 }; 853 }; 854 855 csi2: csi2@10830400 { 856 compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2"; 857 reg = <0 0x10830400 0 0xfc00>; 858 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>, 860 <&cpg CPG_MOD R9A07G054_CRU_VCLK>, 861 <&cpg CPG_MOD R9A07G054_CRU_PCLK>; 862 clock-names = "system", "video", "apb"; 863 resets = <&cpg R9A07G054_CRU_PRESETN>, 864 <&cpg R9A07G054_CRU_CMN_RSTB>; 865 reset-names = "presetn", "cmn-rstb"; 866 power-domains = <&cpg>; 867 status = "disabled"; 868 869 ports { 870 #address-cells = <1>; 871 #size-cells = <0>; 872 873 port@0 { 874 reg = <0>; 875 }; 876 877 port@1 { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 reg = <1>; 881 882 csi2cru: endpoint@0 { 883 reg = <0>; 884 remote-endpoint = <&crucsi2>; 885 }; 886 }; 887 }; 888 }; 889 890 dsi: dsi@10850000 { 891 compatible = "renesas,r9a07g054-mipi-dsi", 892 "renesas,rzg2l-mipi-dsi"; 893 reg = <0 0x10850000 0 0x20000>; 894 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 901 interrupt-names = "seq0", "seq1", "vin1", "rcv", 902 "ferr", "ppi", "debug"; 903 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>, 904 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>, 905 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>, 906 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>, 907 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>, 908 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>; 909 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; 910 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>, 911 <&cpg R9A07G054_MIPI_DSI_ARESET_N>, 912 <&cpg R9A07G054_MIPI_DSI_PRESET_N>; 913 reset-names = "rst", "arst", "prst"; 914 power-domains = <&cpg>; 915 status = "disabled"; 916 917 ports { 918 #address-cells = <1>; 919 #size-cells = <0>; 920 921 port@0 { 922 reg = <0>; 923 dsi0_in: endpoint { 924 remote-endpoint = <&du_out_dsi>; 925 }; 926 }; 927 928 port@1 { 929 reg = <1>; 930 }; 931 }; 932 }; 933 934 vspd: vsp@10870000 { 935 compatible = "renesas,r9a07g054-vsp2", 936 "renesas,r9a07g044-vsp2"; 937 reg = <0 0x10870000 0 0x10000>; 938 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, 940 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, 941 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; 942 clock-names = "aclk", "pclk", "vclk"; 943 power-domains = <&cpg>; 944 resets = <&cpg R9A07G054_LCDC_RESET_N>; 945 renesas,fcp = <&fcpvd>; 946 }; 947 948 fcpvd: fcp@10880000 { 949 compatible = "renesas,r9a07g054-fcpvd", 950 "renesas,fcpv"; 951 reg = <0 0x10880000 0 0x10000>; 952 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, 953 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, 954 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; 955 clock-names = "aclk", "pclk", "vclk"; 956 power-domains = <&cpg>; 957 resets = <&cpg R9A07G054_LCDC_RESET_N>; 958 }; 959 960 du: display@10890000 { 961 compatible = "renesas,r9a07g054-du", 962 "renesas,r9a07g044-du"; 963 reg = <0 0x10890000 0 0x10000>; 964 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>, 966 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>, 967 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>; 968 clock-names = "aclk", "pclk", "vclk"; 969 power-domains = <&cpg>; 970 resets = <&cpg R9A07G054_LCDC_RESET_N>; 971 renesas,vsps = <&vspd 0>; 972 status = "disabled"; 973 974 ports { 975 #address-cells = <1>; 976 #size-cells = <0>; 977 978 port@0 { 979 reg = <0>; 980 du_out_dsi: endpoint { 981 remote-endpoint = <&dsi0_in>; 982 }; 983 }; 984 985 port@1 { 986 reg = <1>; 987 }; 988 }; 989 }; 990 991 cpg: clock-controller@11010000 { 992 compatible = "renesas,r9a07g054-cpg"; 993 reg = <0 0x11010000 0 0x10000>; 994 clocks = <&extal_clk>; 995 clock-names = "extal"; 996 #clock-cells = <2>; 997 #reset-cells = <1>; 998 #power-domain-cells = <0>; 999 }; 1000 1001 sysc: system-controller@11020000 { 1002 compatible = "renesas,r9a07g054-sysc"; 1003 reg = <0 0x11020000 0 0x10000>; 1004 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1008 interrupt-names = "lpm_int", "ca55stbydone_int", 1009 "cm33stbyr_int", "ca55_deny"; 1010 status = "disabled"; 1011 }; 1012 1013 pinctrl: pinctrl@11030000 { 1014 compatible = "renesas,r9a07g054-pinctrl", 1015 "renesas,r9a07g044-pinctrl"; 1016 reg = <0 0x11030000 0 0x10000>; 1017 gpio-controller; 1018 #gpio-cells = <2>; 1019 #interrupt-cells = <2>; 1020 interrupt-parent = <&irqc>; 1021 interrupt-controller; 1022 gpio-ranges = <&pinctrl 0 0 392>; 1023 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; 1024 power-domains = <&cpg>; 1025 resets = <&cpg R9A07G054_GPIO_RSTN>, 1026 <&cpg R9A07G054_GPIO_PORT_RESETN>, 1027 <&cpg R9A07G054_GPIO_SPARE_RESETN>; 1028 }; 1029 1030 irqc: interrupt-controller@110a0000 { 1031 compatible = "renesas,r9a07g054-irqc", 1032 "renesas,rzg2l-irqc"; 1033 #interrupt-cells = <2>; 1034 #address-cells = <0>; 1035 interrupt-controller; 1036 reg = <0 0x110a0000 0 0x10000>; 1037 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 1079 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 1080 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 1081 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 1082 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 1083 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 1084 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1085 interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3", 1086 "irq4", "irq5", "irq6", "irq7", 1087 "tint0", "tint1", "tint2", "tint3", 1088 "tint4", "tint5", "tint6", "tint7", 1089 "tint8", "tint9", "tint10", "tint11", 1090 "tint12", "tint13", "tint14", "tint15", 1091 "tint16", "tint17", "tint18", "tint19", 1092 "tint20", "tint21", "tint22", "tint23", 1093 "tint24", "tint25", "tint26", "tint27", 1094 "tint28", "tint29", "tint30", "tint31", 1095 "bus-err", "ec7tie1-0", "ec7tie2-0", 1096 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1", 1097 "ec7tiovf-1"; 1098 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, 1099 <&cpg CPG_MOD R9A07G054_IA55_PCLK>; 1100 clock-names = "clk", "pclk"; 1101 power-domains = <&cpg>; 1102 resets = <&cpg R9A07G054_IA55_RESETN>; 1103 }; 1104 1105 dmac: dma-controller@11820000 { 1106 compatible = "renesas,r9a07g054-dmac", 1107 "renesas,rz-dmac"; 1108 reg = <0 0x11820000 0 0x10000>, 1109 <0 0x11830000 0 0x10000>; 1110 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 1111 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 1112 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 1113 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 1114 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 1115 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 1116 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 1117 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 1118 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 1119 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 1120 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 1121 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 1122 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1123 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 1124 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 1125 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 1126 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 1127 interrupt-names = "error", 1128 "ch0", "ch1", "ch2", "ch3", 1129 "ch4", "ch5", "ch6", "ch7", 1130 "ch8", "ch9", "ch10", "ch11", 1131 "ch12", "ch13", "ch14", "ch15"; 1132 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, 1133 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; 1134 clock-names = "main", "register"; 1135 power-domains = <&cpg>; 1136 resets = <&cpg R9A07G054_DMAC_ARESETN>, 1137 <&cpg R9A07G054_DMAC_RST_ASYNC>; 1138 reset-names = "arst", "rst_async"; 1139 #dma-cells = <1>; 1140 dma-channels = <16>; 1141 }; 1142 1143 gpu: gpu@11840000 { 1144 compatible = "renesas,r9a07g054-mali", 1145 "arm,mali-bifrost"; 1146 reg = <0x0 0x11840000 0x0 0x10000>; 1147 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1151 interrupt-names = "job", "mmu", "gpu", "event"; 1152 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, 1153 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, 1154 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; 1155 clock-names = "gpu", "bus", "bus_ace"; 1156 power-domains = <&cpg>; 1157 resets = <&cpg R9A07G054_GPU_RESETN>, 1158 <&cpg R9A07G054_GPU_AXI_RESETN>, 1159 <&cpg R9A07G054_GPU_ACE_RESETN>; 1160 reset-names = "rst", "axi_rst", "ace_rst"; 1161 operating-points-v2 = <&gpu_opp_table>; 1162 }; 1163 1164 gic: interrupt-controller@11900000 { 1165 compatible = "arm,gic-v3"; 1166 #interrupt-cells = <3>; 1167 #address-cells = <0>; 1168 interrupt-controller; 1169 reg = <0x0 0x11900000 0 0x20000>, 1170 <0x0 0x11940000 0 0x40000>; 1171 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1172 }; 1173 1174 sdhi0: mmc@11c00000 { 1175 compatible = "renesas,sdhi-r9a07g054", 1176 "renesas,rzg2l-sdhi"; 1177 reg = <0x0 0x11c00000 0 0x10000>; 1178 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, 1181 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, 1182 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, 1183 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; 1184 clock-names = "core", "clkh", "cd", "aclk"; 1185 resets = <&cpg R9A07G054_SDHI0_IXRST>; 1186 power-domains = <&cpg>; 1187 status = "disabled"; 1188 }; 1189 1190 sdhi1: mmc@11c10000 { 1191 compatible = "renesas,sdhi-r9a07g054", 1192 "renesas,rzg2l-sdhi"; 1193 reg = <0x0 0x11c10000 0 0x10000>; 1194 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, 1197 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, 1198 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, 1199 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; 1200 clock-names = "core", "clkh", "cd", "aclk"; 1201 resets = <&cpg R9A07G054_SDHI1_IXRST>; 1202 power-domains = <&cpg>; 1203 status = "disabled"; 1204 }; 1205 1206 eth0: ethernet@11c20000 { 1207 compatible = "renesas,r9a07g054-gbeth", 1208 "renesas,rzg2l-gbeth"; 1209 reg = <0 0x11c20000 0 0x10000>; 1210 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1213 interrupt-names = "mux", "fil", "arp_ns"; 1214 phy-mode = "rgmii"; 1215 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, 1216 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, 1217 <&cpg CPG_CORE R9A07G054_CLK_HP>; 1218 clock-names = "axi", "chi", "refclk"; 1219 resets = <&cpg R9A07G054_ETH0_RST_HW_N>; 1220 power-domains = <&cpg>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 eth1: ethernet@11c30000 { 1227 compatible = "renesas,r9a07g054-gbeth", 1228 "renesas,rzg2l-gbeth"; 1229 reg = <0 0x11c30000 0 0x10000>; 1230 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1233 interrupt-names = "mux", "fil", "arp_ns"; 1234 phy-mode = "rgmii"; 1235 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, 1236 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, 1237 <&cpg CPG_CORE R9A07G054_CLK_HP>; 1238 clock-names = "axi", "chi", "refclk"; 1239 resets = <&cpg R9A07G054_ETH1_RST_HW_N>; 1240 power-domains = <&cpg>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 phyrst: usbphy-ctrl@11c40000 { 1247 compatible = "renesas,r9a07g054-usbphy-ctrl", 1248 "renesas,rzg2l-usbphy-ctrl"; 1249 reg = <0 0x11c40000 0 0x10000>; 1250 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; 1251 resets = <&cpg R9A07G054_USB_PRESETN>; 1252 power-domains = <&cpg>; 1253 #reset-cells = <1>; 1254 status = "disabled"; 1255 1256 usb0_vbus_otg: regulator-vbus { 1257 regulator-name = "vbus"; 1258 }; 1259 }; 1260 1261 ohci0: usb@11c50000 { 1262 compatible = "generic-ohci"; 1263 reg = <0 0x11c50000 0 0x100>; 1264 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1265 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1266 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 1267 resets = <&phyrst 0>, 1268 <&cpg R9A07G054_USB_U2H0_HRESETN>; 1269 phys = <&usb2_phy0 1>; 1270 phy-names = "usb"; 1271 power-domains = <&cpg>; 1272 status = "disabled"; 1273 }; 1274 1275 ohci1: usb@11c70000 { 1276 compatible = "generic-ohci"; 1277 reg = <0 0x11c70000 0 0x100>; 1278 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1280 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 1281 resets = <&phyrst 1>, 1282 <&cpg R9A07G054_USB_U2H1_HRESETN>; 1283 phys = <&usb2_phy1 1>; 1284 phy-names = "usb"; 1285 power-domains = <&cpg>; 1286 status = "disabled"; 1287 }; 1288 1289 ehci0: usb@11c50100 { 1290 compatible = "generic-ehci"; 1291 reg = <0 0x11c50100 0 0x100>; 1292 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1293 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1294 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 1295 resets = <&phyrst 0>, 1296 <&cpg R9A07G054_USB_U2H0_HRESETN>; 1297 phys = <&usb2_phy0 2>; 1298 phy-names = "usb"; 1299 companion = <&ohci0>; 1300 power-domains = <&cpg>; 1301 status = "disabled"; 1302 }; 1303 1304 ehci1: usb@11c70100 { 1305 compatible = "generic-ehci"; 1306 reg = <0 0x11c70100 0 0x100>; 1307 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1309 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 1310 resets = <&phyrst 1>, 1311 <&cpg R9A07G054_USB_U2H1_HRESETN>; 1312 phys = <&usb2_phy1 2>; 1313 phy-names = "usb"; 1314 companion = <&ohci1>; 1315 power-domains = <&cpg>; 1316 status = "disabled"; 1317 }; 1318 1319 usb2_phy0: usb-phy@11c50200 { 1320 compatible = "renesas,usb2-phy-r9a07g054", 1321 "renesas,rzg2l-usb2-phy"; 1322 reg = <0 0x11c50200 0 0x700>; 1323 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1324 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1325 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; 1326 resets = <&phyrst 0>; 1327 #phy-cells = <1>; 1328 power-domains = <&cpg>; 1329 status = "disabled"; 1330 }; 1331 1332 usb2_phy1: usb-phy@11c70200 { 1333 compatible = "renesas,usb2-phy-r9a07g054", 1334 "renesas,rzg2l-usb2-phy"; 1335 reg = <0 0x11c70200 0 0x700>; 1336 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1338 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; 1339 resets = <&phyrst 1>; 1340 #phy-cells = <1>; 1341 power-domains = <&cpg>; 1342 status = "disabled"; 1343 }; 1344 1345 hsusb: usb@11c60000 { 1346 compatible = "renesas,usbhs-r9a07g054", 1347 "renesas,rzg2l-usbhs"; 1348 reg = <0 0x11c60000 0 0x10000>; 1349 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 1350 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1353 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, 1354 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; 1355 resets = <&phyrst 0>, 1356 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; 1357 renesas,buswait = <7>; 1358 phys = <&usb2_phy0 3>; 1359 phy-names = "usb"; 1360 power-domains = <&cpg>; 1361 status = "disabled"; 1362 }; 1363 1364 wdt0: watchdog@12800800 { 1365 compatible = "renesas,r9a07g054-wdt", 1366 "renesas,rzg2l-wdt"; 1367 reg = <0 0x12800800 0 0x400>; 1368 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, 1369 <&cpg CPG_MOD R9A07G054_WDT0_CLK>; 1370 clock-names = "pclk", "oscclk"; 1371 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1373 interrupt-names = "wdt", "perrout"; 1374 resets = <&cpg R9A07G054_WDT0_PRESETN>; 1375 power-domains = <&cpg>; 1376 status = "disabled"; 1377 }; 1378 1379 wdt1: watchdog@12800c00 { 1380 compatible = "renesas,r9a07g054-wdt", 1381 "renesas,rzg2l-wdt"; 1382 reg = <0 0x12800C00 0 0x400>; 1383 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, 1384 <&cpg CPG_MOD R9A07G054_WDT1_CLK>; 1385 clock-names = "pclk", "oscclk"; 1386 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1388 interrupt-names = "wdt", "perrout"; 1389 resets = <&cpg R9A07G054_WDT1_PRESETN>; 1390 power-domains = <&cpg>; 1391 status = "disabled"; 1392 }; 1393 1394 ostm0: timer@12801000 { 1395 compatible = "renesas,r9a07g054-ostm", 1396 "renesas,ostm"; 1397 reg = <0x0 0x12801000 0x0 0x400>; 1398 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 1399 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; 1400 resets = <&cpg R9A07G054_OSTM0_PRESETZ>; 1401 power-domains = <&cpg>; 1402 status = "disabled"; 1403 }; 1404 1405 ostm1: timer@12801400 { 1406 compatible = "renesas,r9a07g054-ostm", 1407 "renesas,ostm"; 1408 reg = <0x0 0x12801400 0x0 0x400>; 1409 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 1410 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; 1411 resets = <&cpg R9A07G054_OSTM1_PRESETZ>; 1412 power-domains = <&cpg>; 1413 status = "disabled"; 1414 }; 1415 1416 ostm2: timer@12801800 { 1417 compatible = "renesas,r9a07g054-ostm", 1418 "renesas,ostm"; 1419 reg = <0x0 0x12801800 0x0 0x400>; 1420 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 1421 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; 1422 resets = <&cpg R9A07G054_OSTM2_PRESETZ>; 1423 power-domains = <&cpg>; 1424 status = "disabled"; 1425 }; 1426 }; 1427 1428 thermal-zones { 1429 cpu-thermal { 1430 polling-delay-passive = <250>; 1431 polling-delay = <1000>; 1432 thermal-sensors = <&tsu 0>; 1433 sustainable-power = <717>; 1434 1435 cooling-maps { 1436 map0 { 1437 trip = <&target>; 1438 cooling-device = <&cpu0 0 2>; 1439 contribution = <1024>; 1440 }; 1441 }; 1442 1443 trips { 1444 sensor_crit: sensor-crit { 1445 temperature = <125000>; 1446 hysteresis = <1000>; 1447 type = "critical"; 1448 }; 1449 1450 target: trip-point { 1451 temperature = <100000>; 1452 hysteresis = <1000>; 1453 type = "passive"; 1454 }; 1455 }; 1456 }; 1457 }; 1458 1459 timer { 1460 compatible = "arm,armv8-timer"; 1461 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1462 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1463 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1464 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1465 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1466 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 1467 "hyp-virt"; 1468 }; 1469}; 1470