1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TI K3 R5F (MCU) Remote Processor driver
4 *
5 * Copyright (C) 2017-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/mailbox_client.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_reserved_mem.h>
18 #include <linux/of_platform.h>
19 #include <linux/omap-mailbox.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/remoteproc.h>
23 #include <linux/reset.h>
24 #include <linux/slab.h>
25
26 #include "omap_remoteproc.h"
27 #include "remoteproc_internal.h"
28 #include "ti_sci_proc.h"
29 #include "ti_k3_common.h"
30
31 /* This address can either be for ATCM or BTCM with the other at address 0x0 */
32 #define K3_R5_TCM_DEV_ADDR 0x41010000
33
34 /* R5 TI-SCI Processor Configuration Flags */
35 #define PROC_BOOT_CFG_FLAG_R5_DBG_EN 0x00000001
36 #define PROC_BOOT_CFG_FLAG_R5_DBG_NIDEN 0x00000002
37 #define PROC_BOOT_CFG_FLAG_R5_LOCKSTEP 0x00000100
38 #define PROC_BOOT_CFG_FLAG_R5_TEINIT 0x00000200
39 #define PROC_BOOT_CFG_FLAG_R5_NMFI_EN 0x00000400
40 #define PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE 0x00000800
41 #define PROC_BOOT_CFG_FLAG_R5_BTCM_EN 0x00001000
42 #define PROC_BOOT_CFG_FLAG_R5_ATCM_EN 0x00002000
43 /* Available from J7200 SoCs onwards */
44 #define PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS 0x00004000
45 /* Applicable to only AM64x SoCs */
46 #define PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE 0x00008000
47
48 /* R5 TI-SCI Processor Control Flags */
49 #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001
50
51 /* R5 TI-SCI Processor Status Flags */
52 #define PROC_BOOT_STATUS_FLAG_R5_WFE 0x00000001
53 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002
54 #define PROC_BOOT_STATUS_FLAG_R5_CLK_GATED 0x00000004
55 #define PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED 0x00000100
56 /* Applicable to only AM64x SoCs */
57 #define PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY 0x00000200
58
59 /*
60 * All cluster mode values are not applicable on all SoCs. The following
61 * are the modes supported on various SoCs:
62 * Split mode : AM65x, J721E, J7200 and AM64x SoCs
63 * LockStep mode : AM65x, J721E and J7200 SoCs
64 * Single-CPU mode : AM64x SoCs only
65 * Single-Core mode : AM62x, AM62A SoCs
66 */
67 enum cluster_mode {
68 CLUSTER_MODE_SPLIT = 0,
69 CLUSTER_MODE_LOCKSTEP,
70 CLUSTER_MODE_SINGLECPU,
71 CLUSTER_MODE_SINGLECORE
72 };
73
74 /**
75 * struct k3_r5_soc_data - match data to handle SoC variations
76 * @tcm_is_double: flag to denote the larger unified TCMs in certain modes
77 * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC
78 * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode
79 * @is_single_core: flag to denote if SoC/IP has only single core R5
80 * @core_data: pointer to R5-core-specific device data
81 */
82 struct k3_r5_soc_data {
83 bool tcm_is_double;
84 bool tcm_ecc_autoinit;
85 bool single_cpu_mode;
86 bool is_single_core;
87 const struct k3_rproc_dev_data *core_data;
88 };
89
90 /**
91 * struct k3_r5_cluster - K3 R5F Cluster structure
92 * @dev: cached device pointer
93 * @mode: Mode to configure the Cluster - Split or LockStep
94 * @cores: list of R5 cores within the cluster
95 * @core_transition: wait queue to sync core state changes
96 * @soc_data: SoC-specific feature data for a R5FSS
97 */
98 struct k3_r5_cluster {
99 struct device *dev;
100 enum cluster_mode mode;
101 struct list_head cores;
102 wait_queue_head_t core_transition;
103 const struct k3_r5_soc_data *soc_data;
104 };
105
106 /**
107 * struct k3_r5_core - K3 R5 core structure
108 * @elem: linked list item
109 * @dev: cached device pointer
110 * @kproc: K3 rproc handle representing this core
111 * @cluster: cached pointer to parent cluster structure
112 * @sram: on-chip SRAM memory regions data
113 * @num_sram: number of on-chip SRAM memory regions
114 * @atcm_enable: flag to control ATCM enablement
115 * @btcm_enable: flag to control BTCM enablement
116 * @loczrama: flag to dictate which TCM is at device address 0x0
117 * @released_from_reset: flag to signal when core is out of reset
118 */
119 struct k3_r5_core {
120 struct list_head elem;
121 struct device *dev;
122 struct k3_rproc *kproc;
123 struct k3_r5_cluster *cluster;
124 struct k3_rproc_mem *sram;
125 int num_sram;
126 u32 atcm_enable;
127 u32 btcm_enable;
128 u32 loczrama;
129 bool released_from_reset;
130 };
131
k3_r5_split_reset(struct k3_rproc * kproc)132 static int k3_r5_split_reset(struct k3_rproc *kproc)
133 {
134 int ret;
135
136 ret = reset_control_assert(kproc->reset);
137 if (ret) {
138 dev_err(kproc->dev, "local-reset assert failed, ret = %d\n",
139 ret);
140 return ret;
141 }
142
143 ret = kproc->ti_sci->ops.dev_ops.put_device(kproc->ti_sci,
144 kproc->ti_sci_id);
145 if (ret) {
146 dev_err(kproc->dev, "module-reset assert failed, ret = %d\n",
147 ret);
148 if (reset_control_deassert(kproc->reset))
149 dev_warn(kproc->dev, "local-reset deassert back failed\n");
150 }
151
152 return ret;
153 }
154
k3_r5_split_release(struct k3_rproc * kproc)155 static int k3_r5_split_release(struct k3_rproc *kproc)
156 {
157 int ret;
158
159 ret = kproc->ti_sci->ops.dev_ops.get_device(kproc->ti_sci,
160 kproc->ti_sci_id);
161 if (ret) {
162 dev_err(kproc->dev, "module-reset deassert failed, ret = %d\n",
163 ret);
164 return ret;
165 }
166
167 ret = reset_control_deassert(kproc->reset);
168 if (ret) {
169 dev_err(kproc->dev, "local-reset deassert failed, ret = %d\n",
170 ret);
171 if (kproc->ti_sci->ops.dev_ops.put_device(kproc->ti_sci,
172 kproc->ti_sci_id))
173 dev_warn(kproc->dev, "module-reset assert back failed\n");
174 }
175
176 return ret;
177 }
178
k3_r5_lockstep_reset(struct k3_r5_cluster * cluster)179 static int k3_r5_lockstep_reset(struct k3_r5_cluster *cluster)
180 {
181 struct k3_r5_core *core;
182 struct k3_rproc *kproc;
183 int ret;
184
185 /* assert local reset on all applicable cores */
186 list_for_each_entry(core, &cluster->cores, elem) {
187 ret = reset_control_assert(core->kproc->reset);
188 if (ret) {
189 dev_err(core->dev, "local-reset assert failed, ret = %d\n",
190 ret);
191 core = list_prev_entry(core, elem);
192 goto unroll_local_reset;
193 }
194 }
195
196 /* disable PSC modules on all applicable cores */
197 list_for_each_entry(core, &cluster->cores, elem) {
198 kproc = core->kproc;
199 ret = kproc->ti_sci->ops.dev_ops.put_device(kproc->ti_sci,
200 kproc->ti_sci_id);
201 if (ret) {
202 dev_err(core->dev, "module-reset assert failed, ret = %d\n",
203 ret);
204 goto unroll_module_reset;
205 }
206 }
207
208 return 0;
209
210 unroll_module_reset:
211 list_for_each_entry_continue_reverse(core, &cluster->cores, elem) {
212 kproc = core->kproc;
213 if (kproc->ti_sci->ops.dev_ops.put_device(kproc->ti_sci,
214 kproc->ti_sci_id))
215 dev_warn(core->dev, "module-reset assert back failed\n");
216 }
217 core = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
218 unroll_local_reset:
219 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
220 if (reset_control_deassert(core->kproc->reset))
221 dev_warn(core->dev, "local-reset deassert back failed\n");
222 }
223
224 return ret;
225 }
226
k3_r5_lockstep_release(struct k3_r5_cluster * cluster)227 static int k3_r5_lockstep_release(struct k3_r5_cluster *cluster)
228 {
229 struct k3_r5_core *core;
230 struct k3_rproc *kproc;
231 int ret;
232
233 /* enable PSC modules on all applicable cores */
234 list_for_each_entry_reverse(core, &cluster->cores, elem) {
235 kproc = core->kproc;
236 ret = kproc->ti_sci->ops.dev_ops.get_device(kproc->ti_sci,
237 kproc->ti_sci_id);
238 if (ret) {
239 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
240 ret);
241 core = list_next_entry(core, elem);
242 goto unroll_module_reset;
243 }
244 }
245
246 /* deassert local reset on all applicable cores */
247 list_for_each_entry_reverse(core, &cluster->cores, elem) {
248 ret = reset_control_deassert(core->kproc->reset);
249 if (ret) {
250 dev_err(core->dev, "module-reset deassert failed, ret = %d\n",
251 ret);
252 goto unroll_local_reset;
253 }
254 }
255
256 return 0;
257
258 unroll_local_reset:
259 list_for_each_entry_continue(core, &cluster->cores, elem) {
260 if (reset_control_assert(core->kproc->reset))
261 dev_warn(core->dev, "local-reset assert back failed\n");
262 }
263 core = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
264 unroll_module_reset:
265 list_for_each_entry_from(core, &cluster->cores, elem) {
266 kproc = core->kproc;
267 if (kproc->ti_sci->ops.dev_ops.put_device(kproc->ti_sci,
268 kproc->ti_sci_id))
269 dev_warn(core->dev, "module-reset assert back failed\n");
270 }
271
272 return ret;
273 }
274
k3_r5_core_halt(struct k3_rproc * kproc)275 static inline int k3_r5_core_halt(struct k3_rproc *kproc)
276 {
277 return ti_sci_proc_set_control(kproc->tsp,
278 PROC_BOOT_CTRL_FLAG_R5_CORE_HALT, 0);
279 }
280
k3_r5_core_run(struct k3_rproc * kproc)281 static inline int k3_r5_core_run(struct k3_rproc *kproc)
282 {
283 return ti_sci_proc_set_control(kproc->tsp,
284 0, PROC_BOOT_CTRL_FLAG_R5_CORE_HALT);
285 }
286
287 /*
288 * The R5F cores have controls for both a reset and a halt/run. The code
289 * execution from DDR requires the initial boot-strapping code to be run
290 * from the internal TCMs. This function is used to release the resets on
291 * applicable cores to allow loading into the TCMs. The .prepare() ops is
292 * invoked by remoteproc core before any firmware loading, and is followed
293 * by the .start() ops after loading to actually let the R5 cores run.
294 *
295 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to
296 * execute code, but combines the TCMs from both cores. The resets for both
297 * cores need to be released to make this possible, as the TCMs are in general
298 * private to each core. Only Core0 needs to be unhalted for running the
299 * cluster in this mode. The function uses the same reset logic as LockStep
300 * mode for this (though the behavior is agnostic of the reset release order).
301 * This callback is invoked only in remoteproc mode.
302 */
k3_r5_rproc_prepare(struct rproc * rproc)303 static int k3_r5_rproc_prepare(struct rproc *rproc)
304 {
305 struct k3_rproc *kproc = rproc->priv;
306 struct k3_r5_core *core = kproc->priv, *core0, *core1;
307 struct k3_r5_cluster *cluster = core->cluster;
308 struct device *dev = kproc->dev;
309 u32 ctrl = 0, cfg = 0, stat = 0;
310 u64 boot_vec = 0;
311 bool mem_init_dis;
312 int ret;
313
314 /*
315 * R5 cores require to be powered on sequentially, core0 should be in
316 * higher power state than core1 in a cluster. So, wait for core0 to
317 * power up before proceeding to core1 and put timeout of 2sec. This
318 * waiting mechanism is necessary because rproc_auto_boot_callback() for
319 * core1 can be called before core0 due to thread execution order.
320 *
321 * By placing the wait mechanism here in .prepare() ops, this condition
322 * is enforced for rproc boot requests from sysfs as well.
323 */
324 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
325 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
326 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1 &&
327 !core0->released_from_reset) {
328 ret = wait_event_interruptible_timeout(cluster->core_transition,
329 core0->released_from_reset,
330 msecs_to_jiffies(2000));
331 if (ret <= 0) {
332 dev_err(dev, "can not power up core1 before core0");
333 return -EPERM;
334 }
335 }
336
337 ret = ti_sci_proc_get_status(kproc->tsp, &boot_vec, &cfg, &ctrl, &stat);
338 if (ret < 0)
339 return ret;
340 mem_init_dis = !!(cfg & PROC_BOOT_CFG_FLAG_R5_MEM_INIT_DIS);
341
342 /* Re-use LockStep-mode reset logic for Single-CPU mode */
343 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
344 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
345 k3_r5_lockstep_release(cluster) : k3_r5_split_release(kproc);
346 if (ret) {
347 dev_err(dev, "unable to enable cores for TCM loading, ret = %d\n",
348 ret);
349 return ret;
350 }
351
352 /*
353 * Notify all threads in the wait queue when core0 state has changed so
354 * that threads waiting for this condition can be executed.
355 */
356 core->released_from_reset = true;
357 if (core == core0)
358 wake_up_interruptible(&cluster->core_transition);
359
360 /*
361 * Newer IP revisions like on J7200 SoCs support h/w auto-initialization
362 * of TCMs, so there is no need to perform the s/w memzero. This bit is
363 * configurable through System Firmware, the default value does perform
364 * auto-init, but account for it in case it is disabled
365 */
366 if (cluster->soc_data->tcm_ecc_autoinit && !mem_init_dis) {
367 dev_dbg(dev, "leveraging h/w init for TCM memories\n");
368 return 0;
369 }
370
371 /*
372 * Zero out both TCMs unconditionally (access from v8 Arm core is not
373 * affected by ATCM & BTCM enable configuration values) so that ECC
374 * can be effective on all TCM addresses.
375 */
376 dev_dbg(dev, "zeroing out ATCM memory\n");
377 memset_io(kproc->mem[0].cpu_addr, 0x00, kproc->mem[0].size);
378
379 dev_dbg(dev, "zeroing out BTCM memory\n");
380 memset_io(kproc->mem[1].cpu_addr, 0x00, kproc->mem[1].size);
381
382 return 0;
383 }
384
385 /*
386 * This function implements the .unprepare() ops and performs the complimentary
387 * operations to that of the .prepare() ops. The function is used to assert the
388 * resets on all applicable cores for the rproc device (depending on LockStep
389 * or Split mode). This completes the second portion of powering down the R5F
390 * cores. The cores themselves are only halted in the .stop() ops, and the
391 * .unprepare() ops is invoked by the remoteproc core after the remoteproc is
392 * stopped.
393 *
394 * The Single-CPU mode on applicable SoCs (eg: AM64x) combines the TCMs from
395 * both cores. The access is made possible only with releasing the resets for
396 * both cores, but with only Core0 unhalted. This function re-uses the same
397 * reset assert logic as LockStep mode for this mode (though the behavior is
398 * agnostic of the reset assert order). This callback is invoked only in
399 * remoteproc mode.
400 */
k3_r5_rproc_unprepare(struct rproc * rproc)401 static int k3_r5_rproc_unprepare(struct rproc *rproc)
402 {
403 struct k3_rproc *kproc = rproc->priv;
404 struct k3_r5_core *core = kproc->priv, *core0, *core1;
405 struct k3_r5_cluster *cluster = core->cluster;
406 struct device *dev = kproc->dev;
407 int ret;
408
409 /*
410 * Ensure power-down of cores is sequential in split mode. Core1 must
411 * power down before Core0 to maintain the expected state. By placing
412 * the wait mechanism here in .unprepare() ops, this condition is
413 * enforced for rproc stop or shutdown requests from sysfs and device
414 * removal as well.
415 */
416 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
417 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
418 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core0 &&
419 core1->released_from_reset) {
420 ret = wait_event_interruptible_timeout(cluster->core_transition,
421 !core1->released_from_reset,
422 msecs_to_jiffies(2000));
423 if (ret <= 0) {
424 dev_err(dev, "can not power down core0 before core1");
425 return -EPERM;
426 }
427 }
428
429 /* Re-use LockStep-mode reset logic for Single-CPU mode */
430 ret = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
431 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
432 k3_r5_lockstep_reset(cluster) : k3_r5_split_reset(kproc);
433 if (ret)
434 dev_err(dev, "unable to disable cores, ret = %d\n", ret);
435
436 /*
437 * Notify all threads in the wait queue when core1 state has changed so
438 * that threads waiting for this condition can be executed.
439 */
440 core->released_from_reset = false;
441 if (core == core1)
442 wake_up_interruptible(&cluster->core_transition);
443
444 return ret;
445 }
446
447 /*
448 * The R5F start sequence includes two different operations
449 * 1. Configure the boot vector for R5F core(s)
450 * 2. Unhalt/Run the R5F core(s)
451 *
452 * The sequence is different between LockStep and Split modes. The LockStep
453 * mode requires the boot vector to be configured only for Core0, and then
454 * unhalt both the cores to start the execution - Core1 needs to be unhalted
455 * first followed by Core0. The Split-mode requires that Core0 to be maintained
456 * always in a higher power state that Core1 (implying Core1 needs to be started
457 * always only after Core0 is started).
458 *
459 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
460 * code, so only Core0 needs to be unhalted. The function uses the same logic
461 * flow as Split-mode for this. This callback is invoked only in remoteproc
462 * mode.
463 */
k3_r5_rproc_start(struct rproc * rproc)464 static int k3_r5_rproc_start(struct rproc *rproc)
465 {
466 struct k3_rproc *kproc = rproc->priv;
467 struct k3_r5_core *core = kproc->priv;
468 struct k3_r5_cluster *cluster = core->cluster;
469 struct device *dev = kproc->dev;
470 u32 boot_addr;
471 int ret;
472
473 boot_addr = rproc->bootaddr;
474 /* TODO: add boot_addr sanity checking */
475 dev_dbg(dev, "booting R5F core using boot addr = 0x%x\n", boot_addr);
476
477 /* boot vector need not be programmed for Core1 in LockStep mode */
478 ret = ti_sci_proc_set_config(kproc->tsp, boot_addr, 0, 0);
479 if (ret)
480 return ret;
481
482 /* unhalt/run all applicable cores */
483 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
484 list_for_each_entry_reverse(core, &cluster->cores, elem) {
485 ret = k3_r5_core_run(core->kproc);
486 if (ret)
487 goto unroll_core_run;
488 }
489 } else {
490 ret = k3_r5_core_run(core->kproc);
491 if (ret)
492 return ret;
493 }
494
495 return 0;
496
497 unroll_core_run:
498 list_for_each_entry_continue(core, &cluster->cores, elem) {
499 if (k3_r5_core_halt(core->kproc))
500 dev_warn(core->dev, "core halt back failed\n");
501 }
502 return ret;
503 }
504
505 /*
506 * The R5F stop function includes the following operations
507 * 1. Halt R5F core(s)
508 *
509 * The sequence is different between LockStep and Split modes, and the order
510 * of cores the operations are performed are also in general reverse to that
511 * of the start function. The LockStep mode requires each operation to be
512 * performed first on Core0 followed by Core1. The Split-mode requires that
513 * Core0 to be maintained always in a higher power state that Core1 (implying
514 * Core1 needs to be stopped first before Core0).
515 *
516 * The Single-CPU mode on applicable SoCs (eg: AM64x) only uses Core0 to execute
517 * code, so only Core0 needs to be halted. The function uses the same logic
518 * flow as Split-mode for this.
519 *
520 * Note that the R5F halt operation in general is not effective when the R5F
521 * core is running, but is needed to make sure the core won't run after
522 * deasserting the reset the subsequent time. The asserting of reset can
523 * be done here, but is preferred to be done in the .unprepare() ops - this
524 * maintains the symmetric behavior between the .start(), .stop(), .prepare()
525 * and .unprepare() ops, and also balances them well between sysfs 'state'
526 * flow and device bind/unbind or module removal. This callback is invoked
527 * only in remoteproc mode.
528 */
k3_r5_rproc_stop(struct rproc * rproc)529 static int k3_r5_rproc_stop(struct rproc *rproc)
530 {
531 struct k3_rproc *kproc = rproc->priv;
532 struct k3_r5_core *core = kproc->priv;
533 struct k3_r5_cluster *cluster = core->cluster;
534 int ret;
535
536 /* halt all applicable cores */
537 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
538 list_for_each_entry(core, &cluster->cores, elem) {
539 ret = k3_r5_core_halt(core->kproc);
540 if (ret) {
541 core = list_prev_entry(core, elem);
542 goto unroll_core_halt;
543 }
544 }
545 } else {
546 ret = k3_r5_core_halt(core->kproc);
547 if (ret)
548 goto out;
549 }
550
551 return 0;
552
553 unroll_core_halt:
554 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
555 if (k3_r5_core_run(core->kproc))
556 dev_warn(core->dev, "core run back failed\n");
557 }
558 out:
559 return ret;
560 }
561
562 /*
563 * Internal Memory translation helper
564 *
565 * Custom function implementing the rproc .da_to_va ops to provide address
566 * translation (device address to kernel virtual address) for internal RAMs
567 * present in a DSP or IPU device). The translated addresses can be used
568 * either by the remoteproc core for loading, or by any rpmsg bus drivers.
569 */
k3_r5_rproc_da_to_va(struct rproc * rproc,u64 da,size_t len,bool * is_iomem)570 static void *k3_r5_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
571 {
572 struct k3_rproc *kproc = rproc->priv;
573 struct k3_r5_core *core = kproc->priv;
574 void __iomem *va = NULL;
575 u32 dev_addr, offset;
576 size_t size;
577 int i;
578
579 if (len == 0)
580 return NULL;
581
582 /* handle any SRAM regions using SoC-view addresses */
583 for (i = 0; i < core->num_sram; i++) {
584 dev_addr = core->sram[i].dev_addr;
585 size = core->sram[i].size;
586
587 if (da >= dev_addr && ((da + len) <= (dev_addr + size))) {
588 offset = da - dev_addr;
589 va = core->sram[i].cpu_addr + offset;
590 return (__force void *)va;
591 }
592 }
593
594 /* handle both TCM and DDR memory regions */
595 return k3_rproc_da_to_va(rproc, da, len, is_iomem);
596 }
597
598 static const struct rproc_ops k3_r5_rproc_ops = {
599 .prepare = k3_r5_rproc_prepare,
600 .unprepare = k3_r5_rproc_unprepare,
601 .start = k3_r5_rproc_start,
602 .stop = k3_r5_rproc_stop,
603 .kick = k3_rproc_kick,
604 .da_to_va = k3_r5_rproc_da_to_va,
605 };
606
607 /*
608 * Internal R5F Core configuration
609 *
610 * Each R5FSS has a cluster-level setting for configuring the processor
611 * subsystem either in a safety/fault-tolerant LockStep mode or a performance
612 * oriented Split mode on most SoCs. A fewer SoCs support a non-safety mode
613 * as an alternate for LockStep mode that exercises only a single R5F core
614 * called Single-CPU mode. Each R5F core has a number of settings to either
615 * enable/disable each of the TCMs, control which TCM appears at the R5F core's
616 * address 0x0. These settings need to be configured before the resets for the
617 * corresponding core are released. These settings are all protected and managed
618 * by the System Processor.
619 *
620 * This function is used to pre-configure these settings for each R5F core, and
621 * the configuration is all done through various ti_sci_proc functions that
622 * communicate with the System Processor. The function also ensures that both
623 * the cores are halted before the .prepare() step.
624 *
625 * The function is called from k3_r5_cluster_rproc_init() and is invoked either
626 * once (in LockStep mode or Single-CPU modes) or twice (in Split mode). Support
627 * for LockStep-mode is dictated by an eFUSE register bit, and the config
628 * settings retrieved from DT are adjusted accordingly as per the permitted
629 * cluster mode. Another eFUSE register bit dictates if the R5F cluster only
630 * supports a Single-CPU mode. All cluster level settings like Cluster mode and
631 * TEINIT (exception handling state dictating ARM or Thumb mode) can only be set
632 * and retrieved using Core0.
633 *
634 * The function behavior is different based on the cluster mode. The R5F cores
635 * are configured independently as per their individual settings in Split mode.
636 * They are identically configured in LockStep mode using the primary Core0
637 * settings. However, some individual settings cannot be set in LockStep mode.
638 * This is overcome by switching to Split-mode initially and then programming
639 * both the cores with the same settings, before reconfiguing again for
640 * LockStep mode.
641 */
k3_r5_rproc_configure(struct k3_rproc * kproc)642 static int k3_r5_rproc_configure(struct k3_rproc *kproc)
643 {
644 struct k3_r5_core *temp, *core0, *core = kproc->priv;
645 struct k3_r5_cluster *cluster = core->cluster;
646 struct device *dev = kproc->dev;
647 u32 ctrl = 0, cfg = 0, stat = 0;
648 u32 set_cfg = 0, clr_cfg = 0;
649 u64 boot_vec = 0;
650 bool lockstep_en;
651 bool single_cpu;
652 int ret;
653
654 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
655 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
656 cluster->mode == CLUSTER_MODE_SINGLECPU ||
657 cluster->mode == CLUSTER_MODE_SINGLECORE) {
658 core = core0;
659 } else {
660 core = kproc->priv;
661 }
662
663 ret = ti_sci_proc_get_status(core->kproc->tsp, &boot_vec, &cfg, &ctrl,
664 &stat);
665 if (ret < 0)
666 return ret;
667
668 dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n",
669 boot_vec, cfg, ctrl, stat);
670
671 single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY);
672 lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED);
673
674 /* Override to single CPU mode if set in status flag */
675 if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) {
676 dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n");
677 cluster->mode = CLUSTER_MODE_SINGLECPU;
678 }
679
680 /* Override to split mode if lockstep enable bit is not set in status flag */
681 if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) {
682 dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n");
683 cluster->mode = CLUSTER_MODE_SPLIT;
684 }
685
686 /* always enable ARM mode and set boot vector to 0 */
687 boot_vec = 0x0;
688 if (core == core0) {
689 clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT;
690 /*
691 * Single-CPU configuration bit can only be configured
692 * on Core0 and system firmware will NACK any requests
693 * with the bit configured, so program it only on
694 * permitted cores
695 */
696 if (cluster->mode == CLUSTER_MODE_SINGLECPU ||
697 cluster->mode == CLUSTER_MODE_SINGLECORE) {
698 set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE;
699 } else {
700 /*
701 * LockStep configuration bit is Read-only on Split-mode
702 * _only_ devices and system firmware will NACK any
703 * requests with the bit configured, so program it only
704 * on permitted devices
705 */
706 if (lockstep_en)
707 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
708 }
709 }
710
711 if (core->atcm_enable)
712 set_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
713 else
714 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_ATCM_EN;
715
716 if (core->btcm_enable)
717 set_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
718 else
719 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_BTCM_EN;
720
721 if (core->loczrama)
722 set_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
723 else
724 clr_cfg |= PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE;
725
726 if (cluster->mode == CLUSTER_MODE_LOCKSTEP) {
727 /*
728 * work around system firmware limitations to make sure both
729 * cores are programmed symmetrically in LockStep. LockStep
730 * and TEINIT config is only allowed with Core0.
731 */
732 list_for_each_entry(temp, &cluster->cores, elem) {
733 ret = k3_r5_core_halt(temp->kproc);
734 if (ret)
735 goto out;
736
737 if (temp != core) {
738 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
739 clr_cfg &= ~PROC_BOOT_CFG_FLAG_R5_TEINIT;
740 }
741 ret = ti_sci_proc_set_config(temp->kproc->tsp, boot_vec,
742 set_cfg, clr_cfg);
743 if (ret)
744 goto out;
745 }
746
747 set_cfg = PROC_BOOT_CFG_FLAG_R5_LOCKSTEP;
748 clr_cfg = 0;
749 ret = ti_sci_proc_set_config(core->kproc->tsp, boot_vec,
750 set_cfg, clr_cfg);
751 } else {
752 ret = k3_r5_core_halt(core->kproc);
753 if (ret)
754 goto out;
755
756 ret = ti_sci_proc_set_config(core->kproc->tsp, boot_vec,
757 set_cfg, clr_cfg);
758 }
759
760 out:
761 return ret;
762 }
763
764 /*
765 * Each R5F core within a typical R5FSS instance has a total of 64 KB of TCMs,
766 * split equally into two 32 KB banks between ATCM and BTCM. The TCMs from both
767 * cores are usable in Split-mode, but only the Core0 TCMs can be used in
768 * LockStep-mode. The newer revisions of the R5FSS IP maximizes these TCMs by
769 * leveraging the Core1 TCMs as well in certain modes where they would have
770 * otherwise been unusable (Eg: LockStep-mode on J7200 SoCs, Single-CPU mode on
771 * AM64x SoCs). This is done by making a Core1 TCM visible immediately after the
772 * corresponding Core0 TCM. The SoC memory map uses the larger 64 KB sizes for
773 * the Core0 TCMs, and the dts representation reflects this increased size on
774 * supported SoCs. The Core0 TCM sizes therefore have to be adjusted to only
775 * half the original size in Split mode.
776 */
k3_r5_adjust_tcm_sizes(struct k3_rproc * kproc)777 static void k3_r5_adjust_tcm_sizes(struct k3_rproc *kproc)
778 {
779 struct k3_r5_core *core0, *core = kproc->priv;
780 struct k3_r5_cluster *cluster = core->cluster;
781 struct device *cdev = core->dev;
782
783 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
784 cluster->mode == CLUSTER_MODE_SINGLECPU ||
785 cluster->mode == CLUSTER_MODE_SINGLECORE ||
786 !cluster->soc_data->tcm_is_double)
787 return;
788
789 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
790 if (core == core0) {
791 WARN_ON(kproc->mem[0].size != SZ_64K);
792 WARN_ON(kproc->mem[1].size != SZ_64K);
793
794 kproc->mem[0].size /= 2;
795 kproc->mem[1].size /= 2;
796
797 dev_dbg(cdev, "adjusted TCM sizes, ATCM = 0x%zx BTCM = 0x%zx\n",
798 kproc->mem[0].size, kproc->mem[1].size);
799 }
800 }
801
802 /*
803 * This function checks and configures a R5F core for IPC-only or remoteproc
804 * mode. The driver is configured to be in IPC-only mode for a R5F core when
805 * the core has been loaded and started by a bootloader. The IPC-only mode is
806 * detected by querying the System Firmware for reset, power on and halt status
807 * and ensuring that the core is running. Any incomplete steps at bootloader
808 * are validated and errored out.
809 *
810 * In IPC-only mode, the driver state flags for ATCM, BTCM and LOCZRAMA settings
811 * and cluster mode parsed originally from kernel DT are updated to reflect the
812 * actual values configured by bootloader. The driver internal device memory
813 * addresses for TCMs are also updated.
814 */
k3_r5_rproc_configure_mode(struct k3_rproc * kproc)815 static int k3_r5_rproc_configure_mode(struct k3_rproc *kproc)
816 {
817 struct k3_r5_core *core0, *core = kproc->priv;
818 struct k3_r5_cluster *cluster = core->cluster;
819 struct device *cdev = core->dev;
820 bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false;
821 u32 ctrl = 0, cfg = 0, stat = 0, halted = 0;
822 u64 boot_vec = 0;
823 u32 atcm_enable, btcm_enable, loczrama;
824 enum cluster_mode mode = cluster->mode;
825 int reset_ctrl_status;
826 int ret;
827
828 core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem);
829
830 ret = kproc->ti_sci->ops.dev_ops.is_on(kproc->ti_sci, kproc->ti_sci_id,
831 &r_state, &c_state);
832 if (ret) {
833 dev_err(cdev, "failed to get initial state, mode cannot be determined, ret = %d\n",
834 ret);
835 return ret;
836 }
837 if (r_state != c_state) {
838 dev_warn(cdev, "R5F core may have been powered on by a different host, programmed state (%d) != actual state (%d)\n",
839 r_state, c_state);
840 }
841
842 reset_ctrl_status = reset_control_status(kproc->reset);
843 if (reset_ctrl_status < 0) {
844 dev_err(cdev, "failed to get initial local reset status, ret = %d\n",
845 reset_ctrl_status);
846 return reset_ctrl_status;
847 }
848
849 /*
850 * Skip the waiting mechanism for sequential power-on of cores if the
851 * core has already been booted by another entity.
852 */
853 core->released_from_reset = c_state;
854
855 ret = ti_sci_proc_get_status(kproc->tsp, &boot_vec, &cfg, &ctrl,
856 &stat);
857 if (ret < 0) {
858 dev_err(cdev, "failed to get initial processor status, ret = %d\n",
859 ret);
860 return ret;
861 }
862 atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0;
863 btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0;
864 loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0;
865 single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0;
866 lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0;
867
868 if (single_cpu && mode != CLUSTER_MODE_SINGLECORE)
869 mode = CLUSTER_MODE_SINGLECPU;
870 if (lockstep_en)
871 mode = CLUSTER_MODE_LOCKSTEP;
872
873 halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT;
874
875 /*
876 * IPC-only mode detection requires both local and module resets to
877 * be deasserted and R5F core to be unhalted. Local reset status is
878 * irrelevant if module reset is asserted (POR value has local reset
879 * deasserted), and is deemed as remoteproc mode
880 */
881 if (c_state && !reset_ctrl_status && !halted) {
882 dev_info(cdev, "configured R5F for IPC-only mode\n");
883 kproc->rproc->state = RPROC_DETACHED;
884 ret = 1;
885 /* override rproc ops with only required IPC-only mode ops */
886 kproc->rproc->ops->prepare = NULL;
887 kproc->rproc->ops->unprepare = NULL;
888 kproc->rproc->ops->start = NULL;
889 kproc->rproc->ops->stop = NULL;
890 kproc->rproc->ops->attach = k3_rproc_attach;
891 kproc->rproc->ops->detach = k3_rproc_detach;
892 kproc->rproc->ops->get_loaded_rsc_table =
893 k3_get_loaded_rsc_table;
894 } else if (!c_state) {
895 dev_info(cdev, "configured R5F for remoteproc mode\n");
896 ret = 0;
897 } else {
898 dev_err(cdev, "mismatched mode: local_reset = %s, module_reset = %s, core_state = %s\n",
899 !reset_ctrl_status ? "deasserted" : "asserted",
900 c_state ? "deasserted" : "asserted",
901 halted ? "halted" : "unhalted");
902 ret = -EINVAL;
903 }
904
905 /* fixup TCMs, cluster & core flags to actual values in IPC-only mode */
906 if (ret > 0) {
907 if (core == core0)
908 cluster->mode = mode;
909 core->atcm_enable = atcm_enable;
910 core->btcm_enable = btcm_enable;
911 core->loczrama = loczrama;
912 kproc->mem[0].dev_addr = loczrama ? 0 : K3_R5_TCM_DEV_ADDR;
913 kproc->mem[1].dev_addr = loczrama ? K3_R5_TCM_DEV_ADDR : 0;
914 }
915
916 return ret;
917 }
918
k3_r5_core_of_get_internal_memories(struct platform_device * pdev,struct k3_rproc * kproc)919 static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
920 struct k3_rproc *kproc)
921 {
922 const struct k3_rproc_dev_data *data = kproc->data;
923 struct device *dev = &pdev->dev;
924 struct k3_r5_core *core = kproc->priv;
925 int num_mems;
926 int i, ret;
927
928 num_mems = data->num_mems;
929 kproc->mem = devm_kcalloc(kproc->dev, num_mems, sizeof(*kproc->mem),
930 GFP_KERNEL);
931 if (!kproc->mem)
932 return -ENOMEM;
933
934 ret = k3_rproc_of_get_memories(pdev, kproc);
935 if (ret)
936 return ret;
937
938 for (i = 0; i < num_mems; i++) {
939 /*
940 * TODO:
941 * The R5F cores can place ATCM & BTCM anywhere in its address
942 * based on the corresponding Region Registers in the System
943 * Control coprocessor. For now, place ATCM and BTCM at
944 * addresses 0 and 0x41010000 (same as the bus address on AM65x
945 * SoCs) based on loczrama setting overriding default assignment
946 * done by k3_rproc_of_get_memories().
947 */
948 if (!strcmp(data->mems[i].name, "atcm")) {
949 kproc->mem[i].dev_addr = core->loczrama ?
950 0 : K3_R5_TCM_DEV_ADDR;
951 } else {
952 kproc->mem[i].dev_addr = core->loczrama ?
953 K3_R5_TCM_DEV_ADDR : 0;
954 }
955
956 dev_dbg(dev, "Updating bus addr %pa of memory %5s\n",
957 &kproc->mem[i].bus_addr, data->mems[i].name);
958 }
959
960 return 0;
961 }
962
k3_r5_core_of_get_sram_memories(struct platform_device * pdev,struct k3_r5_core * core)963 static int k3_r5_core_of_get_sram_memories(struct platform_device *pdev,
964 struct k3_r5_core *core)
965 {
966 struct device_node *np = pdev->dev.of_node;
967 struct device *dev = &pdev->dev;
968 struct device_node *sram_np;
969 struct resource res;
970 int num_sram;
971 int i, ret;
972
973 num_sram = of_property_count_elems_of_size(np, "sram", sizeof(phandle));
974 if (num_sram <= 0) {
975 dev_dbg(dev, "device does not use reserved on-chip memories, num_sram = %d\n",
976 num_sram);
977 return 0;
978 }
979
980 core->sram = devm_kcalloc(dev, num_sram, sizeof(*core->sram), GFP_KERNEL);
981 if (!core->sram)
982 return -ENOMEM;
983
984 for (i = 0; i < num_sram; i++) {
985 sram_np = of_parse_phandle(np, "sram", i);
986 if (!sram_np)
987 return -EINVAL;
988
989 if (!of_device_is_available(sram_np)) {
990 of_node_put(sram_np);
991 return -EINVAL;
992 }
993
994 ret = of_address_to_resource(sram_np, 0, &res);
995 of_node_put(sram_np);
996 if (ret)
997 return -EINVAL;
998
999 core->sram[i].bus_addr = res.start;
1000 core->sram[i].dev_addr = res.start;
1001 core->sram[i].size = resource_size(&res);
1002 core->sram[i].cpu_addr = devm_ioremap_wc(dev, res.start,
1003 resource_size(&res));
1004 if (!core->sram[i].cpu_addr) {
1005 dev_err(dev, "failed to parse and map sram%d memory at %pad\n",
1006 i, &res.start);
1007 return -ENOMEM;
1008 }
1009
1010 dev_dbg(dev, "memory sram%d: bus addr %pa size 0x%zx va %p da 0x%x\n",
1011 i, &core->sram[i].bus_addr,
1012 core->sram[i].size, core->sram[i].cpu_addr,
1013 core->sram[i].dev_addr);
1014 }
1015 core->num_sram = num_sram;
1016
1017 return 0;
1018 }
1019
k3_r5_cluster_rproc_init(struct platform_device * pdev)1020 static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
1021 {
1022 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1023 struct device *dev = &pdev->dev;
1024 struct k3_rproc *kproc;
1025 struct k3_r5_core *core, *core1;
1026 struct device_node *np;
1027 struct device *cdev;
1028 const char *fw_name;
1029 struct rproc *rproc;
1030 int ret, ret1;
1031
1032 core1 = list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1033 list_for_each_entry(core, &cluster->cores, elem) {
1034 cdev = core->dev;
1035 np = dev_of_node(cdev);
1036 ret = rproc_of_parse_firmware(cdev, 0, &fw_name);
1037 if (ret) {
1038 dev_err(dev, "failed to parse firmware-name property, ret = %d\n",
1039 ret);
1040 goto out;
1041 }
1042
1043 rproc = devm_rproc_alloc(cdev, dev_name(cdev), &k3_r5_rproc_ops,
1044 fw_name, sizeof(*kproc));
1045 if (!rproc) {
1046 ret = -ENOMEM;
1047 goto out;
1048 }
1049
1050 /* K3 R5s have a Region Address Translator (RAT) but no MMU */
1051 rproc->has_iommu = false;
1052 /* error recovery is not supported at present */
1053 rproc->recovery_disabled = true;
1054
1055 kproc = rproc->priv;
1056 kproc->priv = core;
1057 kproc->dev = cdev;
1058 kproc->rproc = rproc;
1059 kproc->data = cluster->soc_data->core_data;
1060 core->kproc = kproc;
1061
1062 kproc->ti_sci = devm_ti_sci_get_by_phandle(cdev, "ti,sci");
1063 if (IS_ERR(kproc->ti_sci)) {
1064 ret = dev_err_probe(cdev, PTR_ERR(kproc->ti_sci),
1065 "failed to get ti-sci handle\n");
1066 kproc->ti_sci = NULL;
1067 goto out;
1068 }
1069
1070 ret = of_property_read_u32(np, "ti,sci-dev-id", &kproc->ti_sci_id);
1071 if (ret) {
1072 dev_err(cdev, "missing 'ti,sci-dev-id' property\n");
1073 goto out;
1074 }
1075
1076 kproc->reset = devm_reset_control_get_exclusive(cdev, NULL);
1077 if (IS_ERR_OR_NULL(kproc->reset)) {
1078 ret = PTR_ERR_OR_ZERO(kproc->reset);
1079 if (!ret)
1080 ret = -ENODEV;
1081 dev_err_probe(cdev, ret, "failed to get reset handle\n");
1082 goto out;
1083 }
1084
1085 kproc->tsp = ti_sci_proc_of_get_tsp(cdev, kproc->ti_sci);
1086 if (IS_ERR(kproc->tsp)) {
1087 ret = dev_err_probe(cdev, PTR_ERR(kproc->tsp),
1088 "failed to construct ti-sci proc control\n");
1089 goto out;
1090 }
1091
1092 ret = k3_r5_core_of_get_internal_memories(to_platform_device(cdev), kproc);
1093 if (ret) {
1094 dev_err(cdev, "failed to get internal memories, ret = %d\n",
1095 ret);
1096 goto out;
1097 }
1098
1099 ret = ti_sci_proc_request(kproc->tsp);
1100 if (ret < 0) {
1101 dev_err(cdev, "ti_sci_proc_request failed, ret = %d\n", ret);
1102 goto out;
1103 }
1104
1105 ret = devm_add_action_or_reset(cdev, k3_release_tsp, kproc->tsp);
1106 if (ret)
1107 goto out;
1108 }
1109
1110 list_for_each_entry(core, &cluster->cores, elem) {
1111 cdev = core->dev;
1112 kproc = core->kproc;
1113 rproc = kproc->rproc;
1114
1115 ret = k3_rproc_request_mbox(rproc);
1116 if (ret)
1117 return ret;
1118
1119 ret = k3_r5_rproc_configure_mode(kproc);
1120 if (ret < 0)
1121 goto out;
1122 if (ret)
1123 goto init_rmem;
1124
1125 ret = k3_r5_rproc_configure(kproc);
1126 if (ret) {
1127 dev_err(cdev, "initial configure failed, ret = %d\n",
1128 ret);
1129 goto out;
1130 }
1131
1132 init_rmem:
1133 k3_r5_adjust_tcm_sizes(kproc);
1134
1135 ret = k3_reserved_mem_init(kproc);
1136 if (ret) {
1137 dev_err(cdev, "reserved memory init failed, ret = %d\n",
1138 ret);
1139 goto out;
1140 }
1141
1142 ret = devm_rproc_add(cdev, rproc);
1143 if (ret) {
1144 dev_err_probe(cdev, ret, "rproc_add failed\n");
1145 goto out;
1146 }
1147
1148 /* create only one rproc in lockstep, single-cpu or
1149 * single core mode
1150 */
1151 if (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1152 cluster->mode == CLUSTER_MODE_SINGLECPU ||
1153 cluster->mode == CLUSTER_MODE_SINGLECORE)
1154 break;
1155 }
1156
1157 return 0;
1158
1159 err_split:
1160 if (rproc->state == RPROC_ATTACHED) {
1161 ret1 = rproc_detach(rproc);
1162 if (ret1) {
1163 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n",
1164 ret1);
1165 return ret1;
1166 }
1167 }
1168
1169 out:
1170 /* undo core0 upon any failures on core1 in split-mode */
1171 if (cluster->mode == CLUSTER_MODE_SPLIT && core == core1) {
1172 core = list_prev_entry(core, elem);
1173 kproc = core->kproc;
1174 rproc = kproc->rproc;
1175 goto err_split;
1176 }
1177 return ret;
1178 }
1179
k3_r5_cluster_rproc_exit(void * data)1180 static void k3_r5_cluster_rproc_exit(void *data)
1181 {
1182 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1183 struct k3_rproc *kproc;
1184 struct k3_r5_core *core;
1185 struct rproc *rproc;
1186 int ret;
1187
1188 /*
1189 * lockstep mode and single-cpu modes have only one rproc associated
1190 * with first core, whereas split-mode has two rprocs associated with
1191 * each core, and requires that core1 be powered down first
1192 */
1193 core = (cluster->mode == CLUSTER_MODE_LOCKSTEP ||
1194 cluster->mode == CLUSTER_MODE_SINGLECPU) ?
1195 list_first_entry(&cluster->cores, struct k3_r5_core, elem) :
1196 list_last_entry(&cluster->cores, struct k3_r5_core, elem);
1197
1198 list_for_each_entry_from_reverse(core, &cluster->cores, elem) {
1199 kproc = core->kproc;
1200 rproc = kproc->rproc;
1201
1202 if (rproc->state == RPROC_ATTACHED) {
1203 ret = rproc_detach(rproc);
1204 if (ret) {
1205 dev_err(kproc->dev, "failed to detach rproc, ret = %d\n", ret);
1206 return;
1207 }
1208 }
1209
1210 mbox_free_channel(kproc->mbox);
1211 }
1212 }
1213
k3_r5_core_of_init(struct platform_device * pdev)1214 static int k3_r5_core_of_init(struct platform_device *pdev)
1215 {
1216 struct device *dev = &pdev->dev;
1217 struct device_node *np = dev_of_node(dev);
1218 struct k3_r5_core *core;
1219 int ret;
1220
1221 if (!devres_open_group(dev, k3_r5_core_of_init, GFP_KERNEL))
1222 return -ENOMEM;
1223
1224 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
1225 if (!core) {
1226 ret = -ENOMEM;
1227 goto err;
1228 }
1229
1230 core->dev = dev;
1231 /*
1232 * Use SoC Power-on-Reset values as default if no DT properties are
1233 * used to dictate the TCM configurations
1234 */
1235 core->atcm_enable = 0;
1236 core->btcm_enable = 1;
1237 core->loczrama = 1;
1238
1239 ret = of_property_read_u32(np, "ti,atcm-enable", &core->atcm_enable);
1240 if (ret < 0 && ret != -EINVAL) {
1241 dev_err(dev, "invalid format for ti,atcm-enable, ret = %d\n",
1242 ret);
1243 goto err;
1244 }
1245
1246 ret = of_property_read_u32(np, "ti,btcm-enable", &core->btcm_enable);
1247 if (ret < 0 && ret != -EINVAL) {
1248 dev_err(dev, "invalid format for ti,btcm-enable, ret = %d\n",
1249 ret);
1250 goto err;
1251 }
1252
1253 ret = of_property_read_u32(np, "ti,loczrama", &core->loczrama);
1254 if (ret < 0 && ret != -EINVAL) {
1255 dev_err(dev, "invalid format for ti,loczrama, ret = %d\n", ret);
1256 goto err;
1257 }
1258
1259 ret = k3_r5_core_of_get_sram_memories(pdev, core);
1260 if (ret) {
1261 dev_err(dev, "failed to get sram memories, ret = %d\n", ret);
1262 goto err;
1263 }
1264
1265 platform_set_drvdata(pdev, core);
1266 devres_close_group(dev, k3_r5_core_of_init);
1267
1268 return 0;
1269
1270 err:
1271 devres_release_group(dev, k3_r5_core_of_init);
1272 return ret;
1273 }
1274
1275 /*
1276 * free the resources explicitly since driver model is not being used
1277 * for the child R5F devices
1278 */
k3_r5_core_of_exit(struct platform_device * pdev)1279 static void k3_r5_core_of_exit(struct platform_device *pdev)
1280 {
1281 struct device *dev = &pdev->dev;
1282
1283 platform_set_drvdata(pdev, NULL);
1284 devres_release_group(dev, k3_r5_core_of_init);
1285 }
1286
k3_r5_cluster_of_exit(void * data)1287 static void k3_r5_cluster_of_exit(void *data)
1288 {
1289 struct k3_r5_cluster *cluster = platform_get_drvdata(data);
1290 struct platform_device *cpdev;
1291 struct k3_r5_core *core, *temp;
1292
1293 list_for_each_entry_safe_reverse(core, temp, &cluster->cores, elem) {
1294 list_del(&core->elem);
1295 cpdev = to_platform_device(core->dev);
1296 k3_r5_core_of_exit(cpdev);
1297 }
1298 }
1299
k3_r5_cluster_of_init(struct platform_device * pdev)1300 static int k3_r5_cluster_of_init(struct platform_device *pdev)
1301 {
1302 struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
1303 struct device *dev = &pdev->dev;
1304 struct device_node *np = dev_of_node(dev);
1305 struct platform_device *cpdev;
1306 struct k3_r5_core *core;
1307 int ret;
1308
1309 for_each_available_child_of_node_scoped(np, child) {
1310 cpdev = of_find_device_by_node(child);
1311 if (!cpdev) {
1312 ret = -ENODEV;
1313 dev_err(dev, "could not get R5 core platform device\n");
1314 goto fail;
1315 }
1316
1317 ret = k3_r5_core_of_init(cpdev);
1318 if (ret) {
1319 dev_err(dev, "k3_r5_core_of_init failed, ret = %d\n",
1320 ret);
1321 put_device(&cpdev->dev);
1322 goto fail;
1323 }
1324
1325 core = platform_get_drvdata(cpdev);
1326 core->cluster = cluster;
1327 put_device(&cpdev->dev);
1328 list_add_tail(&core->elem, &cluster->cores);
1329 }
1330
1331 return 0;
1332
1333 fail:
1334 k3_r5_cluster_of_exit(pdev);
1335 return ret;
1336 }
1337
k3_r5_probe(struct platform_device * pdev)1338 static int k3_r5_probe(struct platform_device *pdev)
1339 {
1340 struct device *dev = &pdev->dev;
1341 struct device_node *np = dev_of_node(dev);
1342 struct k3_r5_cluster *cluster;
1343 const struct k3_r5_soc_data *data;
1344 int ret;
1345 int num_cores;
1346
1347 data = of_device_get_match_data(&pdev->dev);
1348 if (!data) {
1349 dev_err(dev, "SoC-specific data is not defined\n");
1350 return -ENODEV;
1351 }
1352
1353 cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
1354 if (!cluster)
1355 return -ENOMEM;
1356
1357 cluster->dev = dev;
1358 cluster->soc_data = data;
1359 INIT_LIST_HEAD(&cluster->cores);
1360 init_waitqueue_head(&cluster->core_transition);
1361
1362 ret = of_property_read_u32(np, "ti,cluster-mode", &cluster->mode);
1363 if (ret < 0 && ret != -EINVAL)
1364 return dev_err_probe(dev, ret, "invalid format for ti,cluster-mode\n");
1365
1366 if (ret == -EINVAL) {
1367 /*
1368 * default to most common efuse configurations - Split-mode on AM64x
1369 * and LockStep-mode on all others
1370 * default to most common efuse configurations -
1371 * Split-mode on AM64x
1372 * Single core on AM62x
1373 * LockStep-mode on all others
1374 */
1375 if (!data->is_single_core)
1376 cluster->mode = data->single_cpu_mode ?
1377 CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP;
1378 else
1379 cluster->mode = CLUSTER_MODE_SINGLECORE;
1380 }
1381
1382 if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) ||
1383 (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core))
1384 return dev_err_probe(dev, -EINVAL,
1385 "Cluster mode = %d is not supported on this SoC\n",
1386 cluster->mode);
1387
1388 num_cores = of_get_available_child_count(np);
1389 if (num_cores != 2 && !data->is_single_core)
1390 return dev_err_probe(dev, -ENODEV,
1391 "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n",
1392 num_cores);
1393
1394 if (num_cores != 1 && data->is_single_core)
1395 return dev_err_probe(dev, -ENODEV,
1396 "SoC supports only single core R5 but num_cores is set to %d\n",
1397 num_cores);
1398
1399 platform_set_drvdata(pdev, cluster);
1400
1401 ret = devm_of_platform_populate(dev);
1402 if (ret)
1403 return dev_err_probe(dev, ret, "devm_of_platform_populate failed\n");
1404
1405 ret = k3_r5_cluster_of_init(pdev);
1406 if (ret)
1407 return dev_err_probe(dev, ret, "k3_r5_cluster_of_init failed\n");
1408
1409 ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
1410 if (ret)
1411 return ret;
1412
1413 ret = k3_r5_cluster_rproc_init(pdev);
1414 if (ret)
1415 return dev_err_probe(dev, ret, "k3_r5_cluster_rproc_init failed\n");
1416
1417 ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
1418 if (ret)
1419 return ret;
1420
1421 return 0;
1422 }
1423
1424 static const struct k3_rproc_mem_data r5_mems[] = {
1425 { .name = "atcm", .dev_addr = 0x0 },
1426 { .name = "btcm", .dev_addr = K3_R5_TCM_DEV_ADDR },
1427 };
1428
1429 static const struct k3_rproc_dev_data r5_data = {
1430 .mems = r5_mems,
1431 .num_mems = ARRAY_SIZE(r5_mems),
1432 .boot_align_addr = 0,
1433 .uses_lreset = true,
1434 };
1435
1436 static const struct k3_r5_soc_data am65_j721e_soc_data = {
1437 .tcm_is_double = false,
1438 .tcm_ecc_autoinit = false,
1439 .single_cpu_mode = false,
1440 .is_single_core = false,
1441 .core_data = &r5_data,
1442 };
1443
1444 static const struct k3_r5_soc_data j7200_j721s2_soc_data = {
1445 .tcm_is_double = true,
1446 .tcm_ecc_autoinit = true,
1447 .single_cpu_mode = false,
1448 .is_single_core = false,
1449 .core_data = &r5_data,
1450 };
1451
1452 static const struct k3_r5_soc_data am64_soc_data = {
1453 .tcm_is_double = true,
1454 .tcm_ecc_autoinit = true,
1455 .single_cpu_mode = true,
1456 .is_single_core = false,
1457 .core_data = &r5_data,
1458 };
1459
1460 static const struct k3_r5_soc_data am62_soc_data = {
1461 .tcm_is_double = false,
1462 .tcm_ecc_autoinit = true,
1463 .single_cpu_mode = false,
1464 .is_single_core = true,
1465 .core_data = &r5_data,
1466 };
1467
1468 static const struct of_device_id k3_r5_of_match[] = {
1469 { .compatible = "ti,am654-r5fss", .data = &am65_j721e_soc_data, },
1470 { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, },
1471 { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, },
1472 { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, },
1473 { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, },
1474 { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, },
1475 { /* sentinel */ },
1476 };
1477 MODULE_DEVICE_TABLE(of, k3_r5_of_match);
1478
1479 static struct platform_driver k3_r5_rproc_driver = {
1480 .probe = k3_r5_probe,
1481 .driver = {
1482 .name = "k3_r5_rproc",
1483 .of_match_table = k3_r5_of_match,
1484 },
1485 };
1486
1487 module_platform_driver(k3_r5_rproc_driver);
1488
1489 MODULE_LICENSE("GPL v2");
1490 MODULE_DESCRIPTION("TI K3 R5F remote processor driver");
1491 MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
1492