Searched refs:NUM_CHANNELS (Results 1 – 5 of 5) sorted by relevance
18 enum { CH_RX, CH_TX, NUM_CHANNELS }; enumerator 36 struct most_channel_capability capabilities[NUM_CHANNELS];74 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in configure_channel() 128 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in enqueue() 173 BUG_ON(ch_idx < 0 || ch_idx >= NUM_CHANNELS); in poison_channel() 303 for (i = 0; i < NUM_CHANNELS; i++) { in i2c_probe() 315 dev->most_iface.num_channels = NUM_CHANNELS; in i2c_probe()
45 #define NUM_CHANNELS 2 /* Max channels */ macro 156 u64 dimm_s_size[NUM_CHANNELS];157 u64 dimm_l_size[NUM_CHANNELS];158 int dimm_l_map[NUM_CHANNELS];1037 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_get_dimm_config() 1104 for (i = 0; i < NUM_CHANNELS; i++) { in igen6_reg_dump() 1244 layers[0].size = NUM_CHANNELS; in igen6_register_mci()
288 #define NUM_CHANNELS 6 /* Max channels per MC */ macro 391 struct pci_dev *pci_tad[NUM_CHANNELS];396 struct sbridge_channel channel[NUM_CHANNELS];1594 : NUM_CHANNELS; in __populate_dimms() 1870 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout() 1890 for (i = 0; i < NUM_CHANNELS; i++) { in get_memory_layout() 2381 if (channel >= NUM_CHANNELS) { in get_memory_error_data_from_mce() 3203 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS); in sbridge_mce_output_error() 3359 KNL_MAX_CHANNELS : NUM_CHANNELS; in sbridge_register_mci()
29 #define NUM_CHANNELS 8 macro
52 #define NUM_CHANNELS ARRAY_SIZE(channel_freq) macro 315 i < NUM_CHANNELS && chs < IW_MAX_FREQUENCIES; i++) in gelic_wl_get_range()