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Searched refs:GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h4315 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x00000005 macro
H A Dgfx_7_2_sh_mask.h14618 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
H A Dgfx_8_0_sh_mask.h16546 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgfx_8_1_sh_mask.h17134 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h4724 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_9_1_sh_mask.h4196 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_9_4_3_sh_mask.h5149 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_9_2_1_sh_mask.h4102 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_9_4_2_sh_mask.h6829 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_10_1_0_sh_mask.h8994 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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H A Dgc_10_3_0_sh_mask.h9171 #define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 macro
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