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Searched refs:DSCEnable (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_utils.c125 dml_output_array->DSCEnable[dst_index] = dml_output_array->DSCEnable[src_index]; in dml2_util_copy_dml_output()
H A Ddisplay_mode_core_structs.h628 enum dml_dsc_enable DSCEnable[__DML_NUM_PLANES__]; //< brief for mode support check; use to determine if dsc is required member
H A Ddml2_translation_helper.c784 out->DSCEnable[location] = (enum dml_dsc_enable)in->timing.flags.DSC; in populate_dml_output_cfg_from_stream_state()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddisplay_mode_vba_314.c3694 bool DSCEnable, argument
3737 if (DSCEnable && Output == dm_dp) {
3750 if (DSCEnable) {
3770 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
3771 || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
4397 if (v->DSCEnable[k] == true) {
4434 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4476 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4517 if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
4632 if (v->DSCEnable[
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddisplay_mode_vba_31.c3588 bool DSCEnable, argument
3631 if (DSCEnable && Output == dm_dp) {
3644 if (DSCEnable) {
3664 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP <= NonDSCBPP0))
3665 || (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {
4310 if (v->DSCEnable[k] == true) {
4347 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4389 v->DSCEnable[k] == true && v->ForcedOutputLinkBPP[k] == 0) {
4430 if (v->Outbpp == BPP_INVALID && v->DSCEnable[k] == true &&
4545 if (v->DSCEnable[
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
H A Ddml2_core_dcn4_calcs.c1263 bool DSCEnable, in TruncToValidBPP() argument
1316 } else if (DSCEnable && Output == dml2_dp) { in TruncToValidBPP()
1322 ODMMode = DSCEnable ? ODMModeDSC : ODMModeNoDSC; in TruncToValidBPP()
1329 if (DSCEnable) { in TruncToValidBPP()
1349 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) || in TruncToValidBPP()
1350 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { in TruncToValidBPP()
4101 bool DSCEnable, in CalculateODMMode() argument
4123 bool UseDSC = DSCEnable && (NumberOfDSCSlices > 0); in CalculateODMMode()
4133 DML_LOG_VERBOSE("DML::%s: DSCEnable = %d\n", __func__, DSCEnable); in CalculateODMMode()
4209 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
4453 RequiredDTBCLK(bool DSCEnable,double PixelClock,enum dml2_output_format_class OutputFormat,double OutputBpp,unsigned int DSCSlices,unsigned int HTotal,unsigned int HActive,unsigned int AudioRate,unsigned int AudioLayout) RequiredDTBCLK() argument
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h1072 bool DSCEnable[DC__NUM_DPP__MAX]; member
H A Ddisplay_mode_vba.c648 mode_lib->vba.DSCEnable[mode_lib->vba.NumberOfActivePlanes] = dout->dsc_enable; in fetch_pipe_params()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c3444 bool DSCEnable, in TruncToValidBPP() argument
3486 if (DSCEnable && Output == dm_dp) { in TruncToValidBPP()
3500 if (DSCEnable) { in TruncToValidBPP()
3520 if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) || in TruncToValidBPP()
3521 (DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) { in TruncToValidBPP()
4066 if (v->DSCEnable[k] == true) { in dml30_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_32.c2105 mode_lib->vba.DSCEnable[k], in dml32_ModeSupportAndSystemConfigurationFull()
2361 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.ForcedOutputLinkBPP[k] != 0) in dml32_ModeSupportAndSystemConfigurationFull()
2363 if (mode_lib->vba.DSCEnable[k] && mode_lib->vba.OutputFormat[k] == dm_n422 in dml32_ModeSupportAndSystemConfigurationFull()